DF2238RTF6 Renesas Electronics America, DF2238RTF6 Datasheet - Page 800
DF2238RTF6
Manufacturer Part Number
DF2238RTF6
Description
MCU 2.2/3V 256K 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2200r
Datasheet
1.DF2238RFA6V.pdf
(1048 pages)
Specifications of DF2238RTF6
Core Processor
H8S/2000
Core Size
16-Bit
Speed
6MHz
Connectivity
I²C, SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
72
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
2.2 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F2238RTF6
HD64F2238RTF6
HD64F2238RTF6
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2238RTF6V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Section 20 Flash Memory (F-ZTAT Version)
mode. The programming control program in boot mode and the user program/erase control
program in user program mode use these operating modes in combination to perform
programming/erasing. Flash memory programming and erasing should be performed in
accordance with the descriptions in section 20.8.1, Program/Program-Verify and section 20.8.2,
Erase/Erase-Verify, respectively.
20.8.1
When writing data or programs to the flash memory, the program/program-verify flowchart shown
in figure 20.11 should be followed. Performing programming operations according to this
flowchart will enable data or programs to be written to the flash memory without subjecting the
chip to voltage stress or sacrificing program data reliability.
1. Programming must be done to an empty address. Do not reprogram an address to which
2. Programming should be carried out 128 bytes at a time. A 128-byte data transfer must be
3. Prepare the following data storage areas in RAM: A 128-byte programming data area, a 128-
4. Consecutively transfer 128 bytes of data in byte units from the reprogramming data area or
5. The time during which the P1 bit is set to 1 is the programming time. Figure 20.11 shows the
6. The watchdog timer (WDT) is set to prevent overprogramming due to program runaway, etc.
7. For a dummy write to a verify address, write 1-byte data H'FF to an address whose lower 1 bit
8. The maximum number of repetitions of the program/program-verify sequence of the same bit
Rev. 6.00 Mar. 18, 2010 Page 738 of 982
REJ09B0054-0600
programming has already been performed.
performed even if writing fewer than 128 bytes. In this case, H'FF data must be written to the
extra addresses.
byte reprogramming data area, and a 128-byte additional-programming data area. Perform
reprogramming data computation and additional programming data computation according to
figure 20.11.
additional-programming data area to the flash memory. The program address and 128-byte
data are latched in the flash memory. The lower 8 bits of the start address in the flash memory
destination area must be H'00 or H'80.
allowable programming times.
Set a value greater than (t
are B'0. Verify data can be read in words from the address to which a dummy write was
performed.
is (N).
Program/Program-Verify
spsu
+ t
sp200
+ t
cp
+ t
cpsu
) µs as the WDT overflow period.
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