HD6417727BP160CV Renesas Electronics America, HD6417727BP160CV Datasheet - Page 321

IC SH MPU ROMLESS 240BGA

HD6417727BP160CV

Manufacturer Part Number
HD6417727BP160CV
Description
IC SH MPU ROMLESS 240BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet

Specifications of HD6417727BP160CV

Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
160MHz
Connectivity
FIFO, SCI, SIO, SmartCard, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
104
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.7 V ~ 2.05 V
Data Converters
A/D 6x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
240-BGA
Package
240CSP
Family Name
SuperH
Maximum Speed
160 MHz
Operating Supply Voltage
1.8|3.3 V
Data Bus Width
32 Bit
Number Of Programmable I/os
104
Interface Type
SCI/USB
On-chip Adc
6-chx10-bit
On-chip Dac
2-chx8-bit
Number Of Timers
4
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-

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Part Number:
HD6417727BP160CV
Manufacturer:
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Section 10 On-Chip Oscillation Circuits
Mode 7: In this mode, the CKIO pin is an input, an external clock is input to this pin, and
undergoes waveform shaping, and also frequency multiplication according to the setting, by PLL
circuit 1 before being supplied to this LSI. In modes 0 to 2, the system clock is generated from the
output of this LSI’s CKIO pin. Consequently, if a large number of ICs are operating on the clock
cycle, the CKIO pin load will be large. This mode, however, assumes a comparatively large-scale
system. If a large number of ICs are operating on the clock cycle, a clock generator with a number
of low-skew clock outputs can be provided, so that the ICs can operate synchronously by
distributing the clocks to each one.
As PLL circuit 1 compensates for fluctuations in the CKIO pin load, this mode is suitable for
connection of synchronous DRAM.
Rev.6.00 Mar. 27, 2009 Page 263 of 1036
REJ09B0254-0600

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