HD6417727BP160CV Renesas Electronics America, HD6417727BP160CV Datasheet - Page 556

IC SH MPU ROMLESS 240BGA

HD6417727BP160CV

Manufacturer Part Number
HD6417727BP160CV
Description
IC SH MPU ROMLESS 240BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet

Specifications of HD6417727BP160CV

Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
160MHz
Connectivity
FIFO, SCI, SIO, SmartCard, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
104
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.7 V ~ 2.05 V
Data Converters
A/D 6x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
240-BGA
Package
240CSP
Family Name
SuperH
Maximum Speed
160 MHz
Operating Supply Voltage
1.8|3.3 V
Data Bus Width
32 Bit
Number Of Programmable I/os
104
Interface Type
SCI/USB
On-chip Adc
6-chx10-bit
On-chip Dac
2-chx8-bit
Number Of Timers
4
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-

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Section 17 Serial Communication Interface (SCI)
Bit 2—Transmit End (TEND): Indicates that when the last bit of a serial character was
transmitted, the SCTDR did not contain valid data, so transmission has ended. TEND is a read-
only bit and cannot be written.
Bit 2: TEND
0
1
Bit 1—Multiprocessor Bit (MPB): Stores the value of the multiprocessor bit in receive data
when a multiprocessor format is selected for receiving in the asynchronous mode. The MPB is a
read-only bit and cannot be written.
Bit 1: MPB
0
1
Note: * If RE is cleared to 0 when a multiprocessor format is selected, the MPB retains its
Bit 0—Multiprocessor Bit Transfer (MPBT): Stores the value of the multiprocessor bit added to
transmit data when a multiprocessor format is selected for transmitting in the asynchronous mode.
The MPBT setting is ignored in the clock synchronous mode, when a multiprocessor format is not
selected, or when the SCI is not transmitting.
Bit 0: MPBT
0
1
Rev.6.00 Mar. 27, 2009 Page 498 of 1036
REJ09B0254-0600
previous value.
Description
Transmission is in progress
[Clear condition]
When TDRE=1 is read and then 0 is written to TDRE.
End of transmission
[Setting conditions]
1. When the chip is reset or enters standby mode
2. When TE is cleared to 0 in the serial control register (SCSCR)
3. If TDRE is 1 when the last bit of a one-byte serial character is transmitted.
Description
Multiprocessor bit value in receive data is 0*
Multiprocessor bit value in receive data is 1
Description
Multiprocessor bit value in transmit data is 0
Multiprocessor bit value in transmit data is 1
(Initial value)
(Initial value)
(Initial value)

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