HD6417750SF167V Renesas Electronics America, HD6417750SF167V Datasheet - Page 336

MPU 3V 16K PB-FREE 208-QFP

HD6417750SF167V

Manufacturer Part Number

HD6417750SF167V

Description

MPU 3V 16K PB-FREE 208-QFP

Manufacturer

Renesas Electronics America

Series

SuperH® SH7750r

Datasheet

1.D6417750RBP240DV.pdf (1164 pages)

Specifications of HD6417750SF167V

Core Processor

SH-4

Core Size

32-Bit

Speed

167MHz

Connectivity

EBI/EMI, FIFO, SCI, SmartCard

Peripherals

DMA, POR, WDT

Number Of I /o

28

Program Memory Type

ROMless

Ram Size

24K x 8

Voltage - Supply (vcc/vdd)

1.6 V ~ 2 V

Oscillator Type

External

Operating Temperature

-20°C ~ 75°C

Package / Case

208-QFP

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Eeprom Size

-

Program Memory Size

-

Data Converters

-

Available stocks

Company

Part Number

Manufacturer

Quantity

Price

Company:

Bonase Electronics (HK) Co., Limited

Bonase Electronics (HK) Co., Limited

Part Number:

HD6417750SF167V

Manufacturer:

INTERSIL

Quantity:

18 720

Company:

BOSTOCK HK LIMITED

BOSTOCK HK LIMITED

Part Number:

HD6417750SF167V

Manufacturer:

Renesas Electronics America

Quantity:

10 000

Current page: 336 of 1164
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Section 8 Pipelining

Rev.7.00 Oct. 10, 2008 Page 250 of 1074

REJ09B0366-0700

Functional

Category

Data transfer

instructions

Fixed-point

arithmetic

instructions

No.

32

33

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Instruction

MOV.W

MOV.L

MOV.B

MOV.W

MOV.L

MOV.B

MOV.W

MOV.L

MOVCA.L R0,@Rn

MOVT

OCBI

OCBP

OCBWB

PREF

SWAP.B

SWAP.W

XTRCT

ADD

ADD

ADDC

ADDV

CMP/EQ

CMP/EQ

CMP/GE

CMP/GT

CMP/HI

CMP/HS

CMP/PL

CMP/PZ

CMP/STR Rm,Rn

DIV0S

R0,@(disp,Rn)

Rm,@(disp,Rn)

Rm,@(R0,Rn)

Rm,@(R0,Rn)

Rm,@(R0,Rn)

R0,@(disp,GBR)

R0,@(disp,GBR)

R0,@(disp,GBR)

Rn

@Rn

@Rn

@Rn

@Rn

Rm,Rn

Rm,Rn

Rm,Rn

Rm,Rn

#imm,Rn

Rm,Rn

Rm,Rn

#imm,R0

Rm,Rn

Rm,Rn

Rm,Rn

Rm,Rn

Rm,Rn

Rn

Rn

Rm,Rn

Instruc-

tion

Group

LS

LS

LS

LS

LS

LS

LS

LS

LS

EX

LS

LS

LS

LS

EX

EX

EX

EX

EX

EX

EX

MT

MT

MT

MT

MT

MT

MT

MT

MT

EX

Issue

Rate

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

Latency

1

1

1

1

1

1

1

1

3–7

1

1–2

1–5

1–5

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

Execu-

tion

Pattern Stage Start Cycles

#2

#2

#2

#2

#2

#3

#3

#3

#12

#1

#10

#11

#11

#2

#1

#1

#1

#1

#1

#1

#1

#1

#1

#1

#1

#1

#1

#1

#1

#1

#1

—

—

—

—

—

—

—

—

—

MA

—

MA

MA

MA

—

—

—

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—

—

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—

—

—

—

—

—

—

—

—

—

—

—

—

—

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4

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4

4

4

—

—

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—

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—

—

—

—

—

—

—

—

—

—

—

Lock

—

—

—

—

—

—

—

—

3–7

—

1–2

1–5

1–5

—

—

—

—

—

—

—

—

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—

—

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