HD6417750SF167V Renesas Electronics America, HD6417750SF167V Datasheet - Page 356

• Manufacturer Part Number: HD6417750SF167V
• Description: MPU 3V 16K PB-FREE 208-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750SF167V

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 167MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 9 Power-Down Modes
9.5
9.5.1
If a SLEEP instruction is executed when the STBY bit in STBCR is set to 1, the chip switches
from the program execution state to standby mode. In standby mode, the on-chip peripheral
modules halt as well as the CPU. Clock output from the CKIO pin is also stopped.
The CPU and cache register contents are retained. Some on-chip peripheral module registers are
initialized. The state of the peripheral module registers in standby mode is shown in table 9.4.
Table 9.4
Module
Interrupt controller
User break controller
Bus state controller
On-chip oscillation circuits
Timer unit
Realtime clock
Direct memory access controller
Serial communication interface
Notes: DMA transfer should be terminated before making a transition to standby mode. Transfer
The procedure for a transition to standby mode is shown below.
1. Clear the TME bit in the WDT timer control register (WTCSR) to 0, and stop the WDT.
2. Set the STBY bit in the STBCR register to 1, then execute a SLEEP instruction.
3. When standby mode is entered and the chip's internal clock stops, a low-level signal is output
Rev.7.00 Oct. 10, 2008 Page 270 of 1074
REJ09B0366-0700
Set the initial value for the up-count in the WDT timer counter (WTCNT), and set the clock to
be used for the up-count in bits CKS2–CKS0 in the WTCSR register.
at the STATUS1 pin, and a high-level signal at the STATUS0 pin.
results are not guaranteed if standby mode is entered during transfer.
*
Standby Mode
Transition to Standby Mode
Not initialized when the realtime clock (RTC) is in use (see section 12, Timer Unit
(TMU)).
State of Registers in Standby Mode
Initialized Registers
—
—
—
—
TSTR register*
—
—
See Appendix A, Address List See Appendix A, Address List
Registers That Retain
Their Contents
All registers
All registers
All registers
All registers
All registers except TSTR
All registers
All registers