HD6417750SF167V Renesas Electronics America, HD6417750SF167V Datasheet - Page 685
HD6417750SF167V
Manufacturer Part Number
HD6417750SF167V
Description
MPU 3V 16K PB-FREE 208-QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet
1.D6417750RBP240DV.pdf
(1164 pages)
Specifications of HD6417750SF167V
Core Processor
SH-4
Core Size
32-Bit
Speed
167MHz
Connectivity
EBI/EMI, FIFO, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
28
Program Memory Type
ROMless
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
1.6 V ~ 2 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
208-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
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14.3.6
The conditions for ending DMA transfer are different for ending on individual channels and for
ending on all channels together. Except for the case where transfer ends when the value in the
DMA transfer count register (DMATCR) reaches 0, the following conditions apply to ending
transfer.
1. Cycle Steal Mode (External Request, On-Chip Peripheral Module Request, Auto-Request)
2. Burst Mode, Edge Detection (External Request, On-Chip Peripheral Module Request, Auto-
3. Burst Mode, Level Detection (External Request)
4. Transfer Suspension Bus Timing
When a transfer end condition is satisfied, acceptance of DMAC transfer requests is
suspended. The DMAC completes transfer for the transfer requests accepted up to the point at
which the transfer end condition was satisfied, then stops.
In cycle steal mode, the operation is the same for both edge and level transfer request
detection.
Request)
The delay between the point at which a transfer end condition is satisfied and the point at
which the DMAC actually stops is the same as in cycle steal mode. In burst mode with edge
detection, only the first transfer request activates the DMAC, but the timing of stop request
(DE = 0 in CHCR, DME = 0 in DMAOR) sampling is the same as the transfer request
sampling timing shown in 4 and 5 under Operation in section 14.3.5, Number of Bus Cycle
States and DREQ Pin Sampling Timing. Therefore, a transfer request is regarded as having
been issued until a stop request is detected, and the corresponding processing is executed
before the DMAC stops.
The delay between the point at which a transfer end condition is satisfied and the point at
which the DMAC actually stops is the same as in cycle steal mode. As in the case of burst
mode with edge detection, the timing of stop request (DE = 0 in CHCR, DME = 0 in DMAOR)
sampling is the same as the transfer request sampling timing shown in 2 and 3 under Operation
in section 14.3.5, Number of Bus Cycle States and DREQ Pin Sampling Timing. Therefore, a
transfer request is regarded as having been issued until a stop request is detected, and the
corresponding processing is executed before the DMAC stops.
Transfer suspension is executed on completion of processing for one transfer unit. In dual
address mode transfer, write cycle processing is executed even if a transfer end condition is
satisfied during the read cycle, and the transfers covered in 1, 2, and 3 above are also executed
before operation is suspended.
Ending DMA Transfer
Section 14 Direct Memory Access Controller (DMAC)
Rev.7.00 Oct. 10, 2008 Page 599 of 1074
REJ09B0366-0700
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