HD6417750SF167V Renesas Electronics America, HD6417750SF167V Datasheet - Page 436

• Manufacturer Part Number: HD6417750SF167V
• Description: MPU 3V 16K PB-FREE 208-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750SF167V

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 167MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 12 Timer Unit (TMU)
12.2.7
TCPR2 is a 32-bit read-only register for use with the input capture function, provided only in
channel 2.
The input capture function is controlled by means of the input capture control bits (ICPE) and
clock edge bits (CKEG) in TCR2. When input capture occurs, the TCNT2 value is copied into
TCPR2. The value is set in TCPR2 only when the ICPF bit in TCR2 is 0.
TCPR2 is not initialized by a power-on or manual reset, or in standby mode.
12.3
Each channel has a 32-bit timer counter (TCNT) that performs count-down operations, and a 32-
bit timer constant register (TCOR). The channels have an auto-reload function that allows cyclic
count operations, and can also perform external event counting. Channel 2 also has an input
capture function.
12.3.1
When one of bits STR0–STR4 is set to 1 in the timer start register (TSTR, TSTR2), the timer
counter (TCNT) for the corresponding channel starts counting. When TCNT underflows, the UNF
flag is set in the corresponding timer control register (TCR). If the UNIE bit in TCR is set to 1 at
this time, an interrupt request is sent to the CPU. At the same time, the value is copied from
TCOR into TCNT, and the count-down continues (auto-reload function).
Rev.7.00 Oct. 10, 2008 Page 350 of 1074
REJ09B0366-0700
Initial value:
Input Capture Register 2 (TCPR2)
Operation
Counter Operation
R/W:
Bit:
31
R
30
R
29
R
· · · · · · · · · · · · ·
Undefined
R
2
R
1
R
0