UPD78F0500AMC-CAB-AX Renesas Electronics America, UPD78F0500AMC-CAB-AX Datasheet - Page 406

• Manufacturer Part Number: UPD78F0500AMC-CAB-AX
• Description: MCU 8BIT 30SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2r

Specifications of UPD78F0500AMC-CAB-AX

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0/Kx2
R01UH0008EJ0401 Rev.4.01
Jul 15, 2010
Notes 1.
Address: FF40H
Symbol
CKS
The frequency that can be used for the peripheral hardware clock (f
supply voltage and product specifications.
Figure 12-4. Format of Clock Output Selection Register (CKS) (78K0/KE2, 78K0/KF2)
(The values shown in the table above are those when f
4.0 V ≤ V
2.7 V ≤ V
1.8 V ≤ V
(Standard products and
(A) grade products only)
BZOE
BZOE
CLOE
CCS3
BCS1
Supply Voltage
<7>
0
1
0
0
1
1
0
1
0
0
0
0
0
0
0
0
1
After reset: 00H
DD
DD
DD
≤ 5.5 V
< 4.0 V
< 2.7 V
Clock division circuit operation stopped. BUZ fixed to low level.
Clock division circuit operation enabled. BUZ output enabled.
Clock division circuit operation stopped. PCL fixed to low level.
Clock division circuit operation enabled. PCL output enabled.
BCS0
CCS2
BCS1
Other than above
6
0
1
0
1
0
0
0
0
1
1
1
1
0
CHAPTER 12 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER
R/W
f
f
f
f
PRS
PRS
PRS
PRS
f
f
f
Conventional-specification Products
PRS
PRS
PRS
CCS1
BCS0
/2
/2
/2
/2
(
5
0
0
1
1
0
0
1
1
0
μ
≤ 20 MHz
≤ 10 MHz
≤ 5 MHz
10
11
12
13
PD78F05xx and 78F05xxD)
BUZ output enable/disable specification
PCL output enable/disable specification
CLOE
CCS0
<4>
0
1
0
1
0
1
0
1
0
BUZ output clock selection
9.77 kHz
4.88 kHz
2.44 kHz
1.22 kHz
f
f
f
f
f
f
f
f
f
Setting prohibited
PRS
PRS
PRS
PRS
PRS
PRS
PRS
PRS
SUB
CCS3
PRS
Note 2
/2
/2
/2
/2
/2
/2
/2
3
f
2
3
4
5
6
7
PRS
= f
32.768 kHz
= 10 MHz
32.768 kHz
PCL output clock selection
XH
f
SUB
(XSEL = 1).)
−
f
f
CCS2
PRS
PRS
=
Expanded-specification Products
(
2
μ
PRS
PD78F05xxA and 78F05xxDA)
≤ 20 MHz
≤ 5 MHz
) differs depending on the power
5 MHz
Note 1
10 MHz
2.5 MHz
1.25 MHz
625 kHz
312.5 kHz
156.25 kHz
78.125 kHz
10 MHz
19.54 kHz
9.77 kHz
4.88 kHz
2.44 kHz
f
PRS
CCS1
=
1
f
PRS
= 20 MHz
−
Note 1
10 MHz
5 MHz
2.5 MHz
1.25 MHz
625 kHz
312.5 kHz
156.25 kHz
Setting
prohibited
20 MHz
f
CCS0
PRS
0
=
Note 3
406