UPD78F0500AMC-CAB-AX Renesas Electronics America, UPD78F0500AMC-CAB-AX Datasheet - Page 436

• Manufacturer Part Number: UPD78F0500AMC-CAB-AX
• Description: MCU 8BIT 30SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2r

Specifications of UPD78F0500AMC-CAB-AX

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0/Kx2
14.3 Registers Controlling Serial Interface UART0
(1) Asynchronous serial interface operation mode register 0 (ASIM0)
R01UH0008EJ0401 Rev.4.01
Jul 15, 2010
Address: FF70H After reset: 01H R/W
Serial interface UART0 is controlled by the following five registers.
• Asynchronous serial interface operation mode register 0 (ASIM0)
• Asynchronous serial interface reception error status register 0 (ASIS0)
• Baud rate generator control register 0 (BRGC0)
• Port mode register 1 (PM1)
• Port register 1 (P1)
Notes 1.
Symbol
ASIM0
This 8-bit register controls the serial communication operations of serial interface UART0.
This register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets this register to 01H.
Figure 14-2. Format of Asynchronous Serial Interface Operation Mode Register 0 (ASIM0) (1/2)
2.
The input from the R
Asynchronous serial interface reception error status register 0 (ASIS0), transmit shift register 0 (TXS0), and
receive buffer register 0 (RXB0) are reset.
POWER0
POWER0
RXE0
TXE0
0
<7>
Note 1
1
0
1
0
1
Disables operation of the internal operation clock (fixes the clock to low level) and asynchronously
resets the internal circuit
Enables operation of the internal operation clock.
Disables transmission (synchronously resets the transmission circuit).
Enables transmission.
Disables reception (synchronously resets the reception circuit).
Enables reception.
TXE0
<6>
X
D0 pin is fixed to high level when POWER0 = 0.
RXE0
<5>
Enables/disables operation of internal operation clock
Note 2
.
PS01
4
Enables/disables transmission
Enables/disables reception
PS00
CHAPTER 14 SERIAL INTERFACE UART0
3
CL0
2
SL0
1
0
1
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