UPD78F0500AMC-CAB-AX Renesas Electronics America, UPD78F0500AMC-CAB-AX Datasheet - Page 479

• Manufacturer Part Number: UPD78F0500AMC-CAB-AX
• Description: MCU 8BIT 30SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2r

Specifications of UPD78F0500AMC-CAB-AX

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0/Kx2
R01UH0008EJ0401 Rev.4.01
Jul 15, 2010
(e) Normal reception
R
Reception is enabled and the R
operation mode register 6 (ASIM6) is set to 1 and then bit 5 (RXE6) of ASIM6 is set to 1.
The 8-bit counter of the baud rate generator starts counting when the falling edge of the R
detected. When the set value of baud rate generator control register 6 (BRGC6) has been counted, the R
input is sampled again (
When the start bit is detected, reception is started, and serial data is sequentially stored in the receive shift
register (RXS6) at the set baud rate. When the stop bit has been received, the reception completion interrupt
(INTSR6) is generated and the data of RXS6 is written to receive buffer register 6 (RXB6). If an overrun error
(OVE6) occurs, however, the receive data is not written to RXB6.
Even if a parity error (PE6) occurs while reception is in progress, reception continues to the reception position of
the stop bit, and a reception error interrupt (INTSR6/INTSRE6) is generated on completion of reception.
Cautions 1. If a reception error occurs, read ASIS6 and then RXB6 to clear the error flag. Otherwise, an
X
D6 (input)
INTSR6
RXB6
2. Reception is always performed with the “number of stop bits = 1”. The second stop bit is
3. Be sure to read asynchronous serial interface reception error status register 6 (ASIS6)
overrun error will occur when the next data is received, and the reception error status will
persist.
ignored.
before reading RXB6.
Figure 15-19. Reception Completion Interrupt Request Timing
Start
in Figure 15-19). If the R
D0
X
D6 pin input is sampled when bit 7 (POWER6) of asynchronous serial interface
D1
D2
D3
X
D4
D6 pin is low level at this time, it is recognized as a start bit.
D5
CHAPTER 15 SERIAL INTERFACE UART6
D6
D7
Parity
Stop
X
D6 pin input is
X
D6 pin
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