UPD78F0500AMC-CAB-AX Renesas Electronics America, UPD78F0500AMC-CAB-AX Datasheet - Page 691

• Manufacturer Part Number: UPD78F0500AMC-CAB-AX
• Description: MCU 8BIT 30SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2r

Specifications of UPD78F0500AMC-CAB-AX

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0/Kx2
23.1 Register for Confirming Reset Source
used to store which source has generated the reset request.
R01UH0008EJ0401 Rev.4.01
Jul 15, 2010
Many internal reset generation sources exist in the 78K0/Kx2 microcontrollers. The reset control flag register (RESF) is
RESF can be read by an 8-bit memory manipulation instruction.
RESET input, reset by power-on-clear (POC) circuit, and reading RESF set RESF to 00H.
The status of RESF when a reset request is generated is shown in Table 23-3.
Address: FFACH
Symbol
RESF
Note The value after reset varies depending on the reset source.
Caution Do not read data by a 1-bit memory manipulation instruction.
Flag
WDTRF
LVIRF
WDTRF
LVIRF
7
0
0
1
0
1
After reset: 00H
Reset Source
Table 23-3. RESF Status When Reset Request Is Generated
Figure 23-5. Format of Reset Control Flag Register (RESF)
Internal reset request is not generated, or RESF is cleared.
Internal reset request is generated.
Internal reset request is not generated, or RESF is cleared.
Internal reset request is generated.
6
0
Note
Cleared (0)
RESET Input
R
5
0
Internal reset request by low-voltage detector (LVI)
Internal reset request by watchdog timer (WDT)
WDTRF
Cleared (0)
Reset by POC
4
3
0
Set (1)
Held
Reset by WDT
CHAPTER 23 RESET FUNCTION
2
0
Held
Set (1)
Reset by LVI
1
0
LVIRF
0
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