UPD78F0500AMC-CAB-AX Renesas Electronics America, UPD78F0500AMC-CAB-AX Datasheet - Page 680

• Manufacturer Part Number: UPD78F0500AMC-CAB-AX
• Description: MCU 8BIT 30SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2r

Specifications of UPD78F0500AMC-CAB-AX

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

<R>
78K0/Kx2
R01UH0008EJ0401 Rev.4.01
Jul 15, 2010
(b) Release by reset signal generation
When the reset signal is generated, STOP mode is released, and then, as in the case with a normal reset
operation, the program is executed after branching to the reset vector address.
Note Oscillation stabilization time is not required when using the external main system clock (f
Remark f
Internal high-speed
(X1 oscillation)
Status of CPU
oscillation clock
system clock
speed system clock.
Reset signal
Status of CPU
×: don’t care
High-speed
Reset signal
Maskable interrupt
request
Reset
X
: X1 clock oscillation frequency
Table 22-4. Operation in Response to Interrupt Request in STOP Mode
(2) When internal high-speed oscillation clock is used as CPU clock
Release Source
(1) When high-speed system clock is used as CPU clock
Normal operation
(internal high-speed
system clock)
Oscillates
Normal operation
(high-speed
oscillation clock)
Oscillates
Figure 22-7. STOP Mode Release by Reset
instruction
STOP
instruction
STOP
MK××
Oscillation stopped
0
0
0
0
0
1
−
Oscillation stopped
STOP mode
STOP mode
PR××
0
0
1
1
1
×
−
IE
Oscillation
0
1
0
×
1
×
×
Starting X1 oscillation is
stopped
period
Reset
specified by software.
Oscillation
stopped
period
Reset
accuracy stabilization
Wait for oscillation
ISP
(11 to 45 s)
Oscillation
processing
×
×
1
0
1
×
×
stopped
(86 to 361 s)
Reset
(11 to 45 s)
processing
CHAPTER 22 STANDBY FUNCTION
Reset
STOP mode held
Reset processing
Next address
instruction execution
Interrupt servicing
execution
Next address
instruction execution
Interrupt servicing
execution
Oscillation stabilization time
(internal high-speed
Normal operation
oscillation clock)
(internal high-speed
Operation
Normal operation
Oscillates
oscillation clock)
(2
Oscillates
11
/f
X
to 2
16
/f
X
)
Note
EXCLK
) as the high-
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