UPD78F0500AMC-CAB-AX Renesas Electronics America, UPD78F0500AMC-CAB-AX Datasheet - Page 565

• Manufacturer Part Number: UPD78F0500AMC-CAB-AX
• Description: MCU 8BIT 30SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2r

Specifications of UPD78F0500AMC-CAB-AX

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0/Kx2
R01UH0008EJ0401 Rev.4.01
Jul 15, 2010
(4) IIC clock selection register 0 (IICCL0)
Address: FFA8H
Condition for clearing (CLD0 = 0)
• When the SCL0 pin is at low level
• When IICE0 = 0 (operation stop)
• Reset
Condition for clearing (DAD0 = 0)
• When the SDA0 pin is at low level
• When IICE0 = 0 (operation stop)
• Reset
Digital filter can be used only in high-speed mode.
In high-speed mode, the transfer clock does not vary regardless of DFC0 bit set (1)/clear (0).
The digital filter is used for noise elimination in high-speed mode.
Symbol
IICCL0
This register is used to set the transfer clock for the I
IICCL0 is set by a 1-bit or 8-bit memory manipulation instruction. However, the CLD0 and DAD0 bits are read-only.
The SMC0, CL01, and CL00 bits are set in combination with bit 0 (CLX0) of IIC function expansion register 0
(IICX0) (see 18.3 (6) I
Set IICCL0 while bit 7 (IICE0) of IIC control register 0 (IICC0) is 0.
Reset signal generation clears IICCL0 to 00H.
Note Bits 4 and 5 are read-only.
Remark
DAD0
SMC0
CLD0
DFC0
0
1
0
1
0
1
0
1
The SCL0 pin was detected at low level.
The SCL0 pin was detected at high level.
The SDA0 pin was detected at low level.
The SDA0 pin was detected at high level.
Operates in standard mode.
Operates in high-speed mode.
Digital filter off.
Digital filter on.
IICE0: Bit 7 of IIC control register 0 (IICC0)
7
0
After reset: 00H
Figure 18-8. Format of IIC Clock Selection Register 0 (IICCL0)
2
C transfer clock setting method).
6
0
Detection of SDA0 pin level (valid only when IICE0 = 1)
Detection of SCL0 pin level (valid only when IICE0 = 1)
CLD0
<5>
R/W
Note
DAD0
Digital filter operation control
<4>
Operation mode switching
2
C bus.
Condition for setting (CLD0 = 1)
• When the SCL0 pin is at high level
Condition for setting (DAD0 = 1)
• When the SDA0 pin is at high level
SMC0
<3>
CHAPTER 18 SERIAL INTERFACE IIC0
DFC0
<2>
CL01
1
CL00
0
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