SAK-XC2764X-40F80L AA Infineon Technologies, SAK-XC2764X-40F80L AA Datasheet
SAK-XC2764X-40F80L AA
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SAK-XC2764X-40F80L AA Summary of contents
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Architecture XC2764X 16/32-Bit Single-Chip Microcontroller with 32-Bit Performance XC2000 Family / Value Line Data Sheet V1.2 2010- ...
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... Infineon Technologies Office. Infineon Technologies components may be used in life-support devices or systems only with the express written approval of Infineon Technologies failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life ...
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Architecture XC2764X 16/32-Bit Single-Chip Microcontroller with 32-Bit Performance XC2000 Family / Value Line Data Sheet V1.2 2010- ...
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... Thermal resistance values corrected. Values apply to 4-layer PCBs only. Trademarks C166™, TriCore™ and DAVE™ are trademarks of Infineon Technologies AG. We Listen to Your Comments Is there any information in this document that you feel is wrong, unclear or missing? Your feedback will help us to continuously improve the quality of this document. ...
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Table of Contents 1 Summary of Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Testing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Single-Chip Microcontroller with 32-Bit Performance XC2764X (XC2000 Family) 1 Summary of Features For a quick overview and easy reference, the features of the XC2764X are summarized here. • High-performance CPU with five-stage pipeline and MPU – 12.5 ns instruction ...
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... SAF-…: -40°C to 85°C – SAK-…: -40°C to 125°C • the package and the type of delivery. For ordering codes for the XC2764X please contact your sales representative or local distributor ...
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... Device Types The following XC2764X device types are available and can be ordered through Infineon’s direct and/or distribution channels. The devices are available for the SAK temperature range only. Table 1 Synopsis of XC2764X Device Types 1) Derivative Flash Memory XC2764X-40FxL 320 Kbytes 16 Kbytes placeholder for available speed grade in MHz ...
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Definition of Feature Variants The XC2764X types are offered with several Flash memory sizes. describe the location of the available Flash memory. Table 2 Continuous Flash Memory Ranges Total Flash Size 320 Kbytes 1) The uppermost 4-Kbyte sector of ...
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E7'FFFFh (EF'FFFFh) Reserved for PSRAM Available PSRAM E0'0000h (E8'0000h) Figure 1 SRAM Allocation Data Sheet XC2000 Family / Value Line Summary of Features 00'DFFFh Available DSRAM Reserved for DSRAM 00'8000h MC_XC_SRAM_ALLOCATION 11 XC2764X V1.2, 2010-04 ...
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General Device Information The XC2764X series (16/32-Bit Single-Chip Microcontroller with 32-Bit Performance part of the Infineon XC2000 Family of full-feature single- chip CMOS microcontrollers. These devices extend the functionality and performance of the C166 Family in terms ...
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Pin Configuration and Definition The pins of the XC2764X are described in detail in functions. For further explanations please refer to the footnotes at the end of the table. The following figure summarizes all pins, showing their locations on ...
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Key to Pin Definitions • Ctrl.: The output signal for a port pin is selected by bit field PC in the associated register Px_IOCRy. Output O0 is selected by setting the respective bit field PC to 1x00 , output O1 ...
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Table 5 Pin Definitions and Functions (cont’d) Pin Symbol Ctrl St/B T3OUT O1 T6OUT O2 TDO_A ESR2_1 St/B EMUX1 O1 U0C1_DOUT O2 U0C0_DOUT O3 TMS_C IH ...
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Table 5 Pin Definitions and Functions (cont’d) Pin Symbol Ctrl DA/A Bit 0 of Port 6, General Purpose Input/Output EMUX0 O1 BRKOUT O3 ADCx_REQG I TyG U1C1_DX0E DA/A Bit ...
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Table 5 Pin Definitions and Functions (cont’d) Pin Symbol Ctrl. 19 P15.6 I ADC1_CH6 AREF AGND 22 P5.0 I ADC0_CH0 I 23 P5.2 I ADC0_CH2 I TDI_A I 24 P5.3 I ADC0_CH3 I ...
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Table 5 Pin Definitions and Functions (cont’d) Pin Symbol Ctrl. 31 P5.9 I ADC0_CH9 I ADC1_CH9 I CC2_T7IN I 32 P5.10 I ADC0_CH10 I ADC1_CH10 I BRKIN_A I CCU61_T13 I HRA 33 P5.11 I ADC0_CH11 I ADC1_CH11 I 34 P5.13 ...
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Table 5 Pin Definitions and Functions (cont’d) Pin Symbol Ctrl St/B AD13 RxDC0C I T5INB St/B TxDC0 O1 AD14 T5EUDB I ESR1_5 I ...
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Table 5 Pin Definitions and Functions (cont’d) Pin Symbol Ctrl St/B CC2_CC25 St/B CS1 OH T4EUDB I ESR1_8 St/B U0C1_DOUT O1 TxDC0 O2 CC2_CC17 O3 / ...
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Table 5 Pin Definitions and Functions (cont’d) Pin Symbol Ctrl St/B U0C0_SELO O1 0 U0C1_SELO O2 1 CC2_CC19 St/B A19 OH U0C0_DX2D I RxDC0D I ESR2_6 ...
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Table 5 Pin Definitions and Functions (cont’d) Pin Symbol Ctrl St/B U0C1_SELO O1 0 U0C0_SELO O2 1 CC2_CC20 St/B A20 OH U0C1_DX2C I RxDC1C I ESR2_7 ...
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Table 5 Pin Definitions and Functions (cont’d) Pin Symbol Ctrl St/B U0C1_DOUT O1 TxDC1 O2 CC2_CC22 St/B A22 OH CLKIN1 I TCK_A St/B U1C0_SCLK O1 OUT ...
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Table 5 Pin Definitions and Functions (cont’d) Pin Symbol Ctrl. 59 P10 St/B U0C1_DOUT O1 CCU60_CC6 O2 0 AD0 CCU60_CC6 I 0INA ESR1_2 I U0C0_DX0A I U0C1_DX0A I 60 P10 St/B ...
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Table 5 Pin Definitions and Functions (cont’d) Pin Symbol Ctrl. 62 P10 St/B U0C0_SCLK O1 OUT CCU60_CC6 O2 2 AD2 CCU60_CC6 I 2INA U0C0_DX1B St/B U1C1_SELO O1 0 ...
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Table 5 Pin Definitions and Functions (cont’d) Pin Symbol Ctrl. 67 P10 St/B CCU60_COU O2 T60 AD3 U0C0_DX2A I U0C1_DX2A St/B U1C1_SCLK O1 OUT U1C0_SELO O2 2 CCU61_COU ...
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Table 5 Pin Definitions and Functions (cont’d) Pin Symbol Ctrl. 70 P10 St/B U0C1_SCLK O1 OUT CCU60_COU O2 T62 AD5 U0C1_DX1B St/B U1C1_DOUT O1 TxDC1 O2 CCU61_COU O3 ...
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Table 5 Pin Definitions and Functions (cont’d) Pin Symbol Ctrl. 73 P10 St/B U0C1_DOUT O1 CCU60_COU O2 T63 AD7 U0C1_DX0B I CCU60_CCP I OS0A T4INB St/B U1C1_DOUT O1 ...
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Table 5 Pin Definitions and Functions (cont’d) Pin Symbol Ctrl. 79 P10 St/B U0C0_MCLK O1 OUT U0C1_SELO O2 0 AD8 CCU60_CCP I OS1A U0C0_DX1C I BRKIN_B I T3EUDB I 80 P10 ...
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Table 5 Pin Definitions and Functions (cont’d) Pin Symbol Ctrl St/B U1C0_SELO ESR2_3 I 82 P10. St/B U0C0_SELO O1 0 CCU60_COU O2 T63 AD10 U0C0_DX2C ...
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Table 5 Pin Definitions and Functions (cont’d) Pin Symbol Ctrl St/B U1C0_SELO O2 6 A10 OH ESR1_4 I CCU61_T12 I HRB 85 P10. St/B U1C0_DOUT O1 TDO_B AD12 OH ...
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Table 5 Pin Definitions and Functions (cont’d) Pin Symbol Ctrl. 89 P10. St/B U1C0_SELO O1 1 U0C1_DOUT ESR2_2 I U0C1_DX0C St/B U1C1_SELO O2 4 A12 OH 91 P10.15 ...
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Table 5 Pin Definitions and Functions (cont’d) Pin Symbol Ctrl. 96 XTAL1 I ESR2_9 I 97 PORST I 98 ESR1 St/B RxDC0E I U1C0_DX0F I U1C0_DX2C I U1C1_DX0C I U1C1_DX2B I 99 ESR0 St/B ...
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Table 5 Pin Definitions and Functions (cont’d) Pin Symbol Ctrl DDPA DDPB 25, 27, 50, 52, 75, 77, 100 26, 51 generate the reference clock output for ...
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Identification Registers The identification registers describe the current version of the XC2764X and of its modules. Table 6 XC2764X Identification Registers Short Name SCU_IDMANUF SCU_IDCHIP SCU_IDMEM SCU_IDPROG JTAG_ID Data Sheet Value Address 1820 00’F07E H H 3001 00’F07C H ...
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Functional Description The architecture of the XC2764X combines advantages of RISC, CISC, and DSP processors with an advanced peripheral subsystem in a well-balanced design. On-chip memory blocks allow the design of compact systems-on-silicon with maximum performance suited for computing, ...
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Memory Subsystem and Organization The memory space of the XC2764X is configured in the von Neumann architecture. In this architecture all internal and external resources, including code memory, data memory, registers and I/O ports, are organized in the same ...
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Table 7 XC2764X Memory Map (cont’d) Address Area Reserved for DSRAM External memory area 1) Accesses to the shaded areas are reserved. In devices with external bus interface these accesses generate external bus accesses. 2) The areas marked with “<” ...
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Kbytes of on-chip Data SRAM (DSRAM) are used for storage of general user data. The DSRAM is accessed via a separate interface and is optimized for data access. Note: The actual size of the DSRAM depends on ...
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Memory Content Protection The contents of on-chip memories can be protected against soft errors (induced e.g. by radiation) by activating the parity mechanism or the Error Correction Code (ECC). The parity mechanism can detect a single-bit error and prevent the ...
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External Bus Controller All external memory access operations are performed by a special on-chip External Bus Controller (EBC). The EBC also controls access to resources connected to the on-chip LXBus (MultiCAN and the USIC modules). The LXBus is an ...
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Central Processing Unit (CPU) The core of the CPU consists of a 5-stage execution pipeline with a 2-stage instruction- fetch pipeline, a 16-bit arithmetic and logic unit (ALU), a 32-bit/40-bit multiply and accumulate unit (MAC), a register-file providing three ...
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With this hardware most XC2764X instructions are executed in a single machine cycle of 12 80-MHz CPU clock. For example, shift and rotate instructions are always processed during one machine cycle, no matter how many bits are shifted. ...
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Memory Protection Unit (MPU) The XC2764X’s Memory Protection Unit (MPU) protects user-specified memory areas from unauthorized read, write, or instruction fetch accesses. The MPU can protect the whole address space including the peripheral area. This completes established mechanisms such ...
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Interrupt System The architecture of the XC2764X supports several mechanisms for fast and flexible response to service requests; these can be generated from various sources internal or external to the microcontroller. Any of these interrupt requests can be programmed ...
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The occurrence of a hardware trap is also indicated by a single bit in the trap flag register (TFR). Unless another higher-priority trap service is in progress, a hardware trap will interrupt any ongoing ...
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Capture/Compare Unit (CC2) The CAPCOM unit supports generation and control of timing sequences channels with a maximum resolution of one system clock cycle (eight cycles in staggered mode). The CAPCOM unit is typically used to ...
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Table 8 Compare Modes (cont’d) Compare Modes Function Mode 2 Interrupt-only compare mode; Only one compare interrupt per timer period is generated Mode 3 Pin set ‘1’ on match; pin reset ‘0’ on compare timer overflow; Only one compare event ...
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CC T7IN T6OUF CC16IO CC17IO CC31IO f CC T6OUF Figure 6 CAPCOM Unit Block Diagram Data Sheet Reload Reg . T7REL T7 Input Timer T7 Control Mode Sixteen Control 16-bit (Capture Capture/ or Compare Compare) Registers T8 Input Timer ...
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Capture/Compare Units CCU6x The XC2764X types feature the CCU60, CCU61 unit(s). CCU6 is a high-resolution capture and compare unit with application-specific modes. It provides inputs to start the timers synchronously, an important feature in devices with several CCU6 modules. ...
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SYS TxHR T12 Interrupts st art T13 Figure 7 CCU6 Block Diagram Timer T12 can work in capture and/or compare mode for its three channels. The modes can also be combined. Timer T13 can work in compare mode only. ...
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General Purpose Timer (GPT12E) Unit The GPT12E unit is a very flexible multifunctional timer/counter structure which can be used for many different timing tasks such as event timing and counting, pulse width and duty cycle measurements, pulse generation, or ...
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T3CON.BPS1 GPT T2IN T2 Mode Control T2EUD T3 T3IN Mode Control T3EUD T4IN T4 Mode Control T4EUD Figure 8 Block Diagram of GPT1 Data Sheet XC2000 Family / Value Line Basic Clock Aux. Timer T2 U/D ...
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With its maximum resolution of 2 system clock cycles, the GPT2 module provides precise event control and time measurement. It includes two timers (T5, T6) and a capture/reload register (CAPREL). Both timers can be clocked with an input clock which ...
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T6CON.BPS2 GPT T5IN Mode T5EUD Control CAPIN CAPREL Mode Control T3IN/ T3EUD Mode T6IN Control T6EUD Figure 9 Block Diagram of GPT2 Data Sheet Basic Clock GPT2 Timer T5 T5 U/D Clear Capture GPT2 CAPREL Reload ...
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Real Time Clock The Real Time Clock (RTC) module of the XC2764X can be clocked with a clock signal selected from internal sources or external sources (pins). The RTC basically consists of a chain of divider blocks: • Selectable ...
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The RTC module can be used for different purposes: • System clock to determine the current time and date • Cyclic time-based interrupt, to provide a system time tick independent of CPU frequency and other resources • 48-bit timer for ...
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A/D Converters For analog signal measurement two 10-bit A/D converters (ADC0, ADC1) with multiplexed input channels and a sample and hold circuit have been integrated on-chip. 4 inputs can be converted by both A/D ...
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Universal Serial Interface Channel Modules (USIC) The XC2764X features the USIC modules USIC0, USIC1. Each module provides two serial communication channels. The Universal Serial Interface Channel (USIC) module is based on a generic data shift and data storage structure ...
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Target Protocols Each USIC channel can receive and transmit data frames with a selectable data word width from bits in each of the following protocols: • UART (asynchronous serial channel) – module capability: maximum baud rate = ...
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MultiCAN Module The MultiCAN module contains independently operating CAN nodes with Full-CAN functionality which are able to exchange Data and Remote Frames using a gateway function. Transmission and reception of CAN frames is handled in accordance with CAN specification ...
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MultiCAN Features • CAN functionality conforming to CAN specification V2.0 B active for each CAN node (compliant to ISO 11898) • Independent CAN nodes • Set of independent message objects (shared by the CAN nodes) • Dedicated control registers for ...
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Clock Generation The Clock Generation Unit can generate the system clock signal from a number of external or internal clock sources: • External clock signals with pad voltage or core voltage levels • External crystal or resonator using the ...
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Parallel Ports The XC2764X provides I/O lines which are organized into 7 input/output ports and 2 input ports. All port lines are bit-addressable, and all input/output lines can be individually (bit-wise) configured via port control registers. ...
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Instruction Set Summary Table 10 lists the instructions of the XC2764X. The addressing modes that can be used with a specific instruction, the function of the instructions, parameters for conditional execution of instructions, and the opcodes for each instruction ...
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Table 10 Instruction Set Summary (cont’d) Mnemonic Description ROL/ROR Rotate left/right direct word GPR ASHR Arithmetic (sign bit) shift right direct word GPR MOV(B) Move word (byte) data MOVBS/Z Move byte operand to word op. with sign/zero extension JMPA/I/R Jump ...
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Table 10 Instruction Set Summary (cont’d) Mnemonic Description NOP Null operation CoMUL/CoMAC Multiply (and accumulate) CoADD/CoSUB Add/Subtract Co(A)SHR (Arithmetic) Shift right CoSHL Shift left CoLOAD/STORE Load accumulator/Store MAC register CoCMP Compare CoMAX/MIN Maximum/Minimum CoABS/CoRND Absolute value/Round accumulator CoMOV Data move ...
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Electrical Parameters The operating range for the XC2764X is defined by its electrical parameters. For proper operation the specified limits must be respected when integrating the device in its target environment. 4.1 General Parameters These parameters are valid for ...
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Operating Conditions The following operating conditions must not be exceeded to ensure correct operation of the XC2764X. All parameters specified in the following sections refer to these operating conditions, unless otherwise noticed. Note: Typical parameter values refer to room ...
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Table 12 Operating Conditions (cont’d) Parameter Overload current coupling factor for digital I/O pins Absolute sum of overload currents Digital core supply voltage Digital supply voltage for IO pads and voltage regulators Digital ground voltage 1) To ensure the stability ...
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Voltage Range definitions The XC2764X timing depends on the supply voltage. If such a dependency exists the timing values are given for 2 voltage areas commonly used. The voltage areas are defined in the following tables. Table 13 Upper ...
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DC Parameters These parameters are static or average values that may be exceeded during switching transitions (e.g. output current). The XC2764X can operate within a wide supply voltage range from 3 5.5 V. However, during operation this ...
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Pullup/Pulldown Device Behavior Most pins of the XC2764X feature pullup or pulldown devices. For some special pins these are fixed; for the port pins they can be selected by the application. The specified current values indicate how to load the ...
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DC Parameters for Upper Voltage Area Keeping signal levels within the limits specified in this table ensures operation without overload conditions. For signal levels outside these specifications, also refer to the specification of the overload current Note: Operating Conditions ...
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Table 15 DC Characteristics for Upper Voltage Range (cont’d) Parameter 7) Output High voltage 7) Output Low Voltage 1) Because each double bond pin is connected to two pads (standard pad and high-speed pad), it has twice the normal value. ...
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DC Parameters for Lower Voltage Area Keeping signal levels within the limits specified in this table ensures operation without overload conditions. For signal levels outside these specifications, also refer to the specification of the overload current Note: Operating Conditions ...
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Table 16 DC Characteristics for Lower Voltage Range (cont’d) Parameter 7) Output High voltage 7) Output Low Voltage 1) Because each double bond pin is connected to two pads (standard pad and high-speed pad), it has twice the normal value. ...
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Power Consumption The power consumed by the XC2764X depends on several factors such as supply voltage, operating frequency, active circuits, and operating temperature. The power consumption specified here consists of two components: • The switching current • The leakage ...
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Table 17 Switching Power Consumption Parameter Power supply current (active) with all peripherals active and EVVRs on Power supply current in stopover mode, EVVRs MHz SYS 2) The pad supply voltage pins ( consumed by the ...
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I [mA] S 100 Figure 14 Supply Current in Active Mode as a Function of Frequency Note: Operating Conditions apply. Table 18 Leakage Power Consumption Parameter 1) Leakage supply current ...
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Note: A fraction of the leakage current flows through domain DMP_A (pin current can be calculated as 7,000 For T = 150°C, this results in a current of 160 J The leakage power consumption can be calculated according to the ...
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Analog/Digital Converter Parameters These parameters describe the conditions for optimum ADC performance. Note: Operating Conditions apply. Table 19 ADC Parameters Parameter Switched capacitance at an analog input Total capacitance at an analog input Switched capacitance at the reference input ...
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Table 19 ADC Parameters (cont’d) Parameter Broken wire detection 2) delay against VAGND Broken wire detection 2) delay against VAREF Conversion time for 8-bit 2) result Conversion time for 10-bit 2) result Total Unadjusted Error Wakeup time from analog powerdown, ...
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The broken wire detection delay against conversion rate of not more than 10 μs. This function is influenced by leakage current, in particular at high temperature. Result above 80% (332 5) TUE is tested AREF ...
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Sample time and conversion time of the XC2764X’s A/D converters are programmable. The timing above can be calculated using The limit values for f must not be exceeded when selecting the prescaler value. ADCI Table 20 A/D Converter Computation Table ...
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System Parameters The following parameters specify several aspects which are important when integrating the XC2764X into an application system. Note: These parameters are not subject to production test but verified by design and/or characterization. Note: Operating Conditions apply. Table ...
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Conditions for Timing Measurement SSO The time required for the transition from Stopover to Stopover Waked-Up mode is called measured under the following conditions: SSO Precondition: The Stopover mode has been entered using the procedure ...
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Table 22 Coding of bit fields LEVxV in Register SWDCON0 Code Default Voltage Level 0000 2 0001 3 0010 3 0011 3 0100 3 0101 3 0110 3.6 ...
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Flash Memory Parameters The XC2764X is delivered with all Flash sectors erased and with no protection installed. The data retention time of the XC2764X’s Flash memory (i.e. the time after which stored data can still be retrieved) depends on ...
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The unused Flash module(s) can be erased/programmed while code is executed and/or data is read from only one Flash module or from PSRAM. The Flash module that delivers code/data can, of course, not be erased/programmed. 2) Flash module 1 ...
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AC Parameters These parameters describe the dynamic behavior of the XC2764X. 4.7.1 Testing Waveforms These values are used for characterization and production testing (except pin XTAL1). Output delay Hold time 0.8 V DDP 0.7 V DDP 0.3 V DDP ...
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Definition of Internal Timing The internal operation of the XC2764X is controlled by the internal system clock Because the system clock signal external sources using different mechanisms, the duration of the system clock periods (TCSs) and their variation (as ...
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Direct Drive When direct drive operation is selected (SYSCON0.CLKSEL = 11 derived directly from the input clock signal CLKIN1 SYS IN f The frequency of is the same as the frequency of SYS times of f ...
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The timing in the AC Characteristics refers to TCSs. Timing must be calculated using the minimum TCS possible under the given circumstances. The actual minimum value for TCS depends on the jitter of the PLL. Because the PLL is constantly ...
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Acc. jitter ±9 ±8 ±7 ±6 ±5 ±4 ±3 ±2 ± Figure 20 Approximated Accumulated PLL Jitter Note: The specified PLL jitter values are valid if the capacitive load per pin does not C ...
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Table 25 System PLL Parameters Parameter VCO output frequency 4.7.2.2 Wakeup Clock When wakeup operation is selected (SYSCON0.CLKSEL = 00 derived from the low-frequency wakeup clock source SYS WU In this mode, a basic functionality can ...
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To avoid the indicated problems, recommended sequences are provided which ensure the intended operation of the clock system interacting with the power system. Please refer to the Programmer’s Guide. Data Sheet XC2000 Family / Value Line Electrical Parameters 97 XC2764X ...
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External Clock Input Parameters These parameters specify the external clock generation for the XC2764X. The clock can be generated in two ways: • By connecting a crystal or ceramic resonator to pins XTAL1/XTAL2. • By supplying an external clock ...
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V 1) The amplitude voltage AX1 operation and the resulting voltage peaks must remain within the limits defined by 2) Overload conditions must not occur on pin XTAL1 OFF AX1 Figure 21 External Clock Drive XTAL1 Note: ...
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Pad Properties The output pad drivers of the XC2764X can operate in several user-selectable modes. Strong driver mode allows controlling external components requiring higher currents such as power bridges or LEDs. Reducing the driving power of an output pad ...
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Table 27 Standard Pad Parameters for Upper Voltage Range (cont’d) Parameter Rise and Fall times (10 output current above | I OXnom neighboring output pins, the total output current in each direction (Σ Data Sheet Symbol ...
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Table 28 Standard Pad Parameters for Lower Voltage Range Parameter Maximum output driver 1) current (absolute value) Nominal output driver current (absolute value) Data Sheet Symbol Values Min. Typ. − − I Omax CC − − − − − − ...
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Table 28 Standard Pad Parameters for Lower Voltage Range (cont’d) Parameter Rise and Fall times (10 output current above | I OXnom neighboring output pins, the total output current in each direction (Σ Data Sheet Symbol ...
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External Bus Timing The following parameters specify the behavior of the XC2764X bus interface. Note: These parameters are not subject to production test but verified by design and/or characterization. Note: Operating Conditions apply. Table 29 Parameters Parameter 1) CLKOUT ...
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Variable Memory Cycles External bus cycles of the XC2764X are executed in five consecutive cycle phases (AB F). The duration of each cycle phase is programmable (via the TCONCSx registers) to adapt the external bus cycles to ...
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Table 31 External Bus Timing for Upper Voltage Range (cont’d) Parameter Address output valid delay for AD15 ... AD0 (MUX mode) Output valid delay for CS Data output valid delay for AD15 ... AD0 (write data, MUX mode) Data output ...
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Table 32 External Bus Timing for Lower Voltage Range Parameter Output valid delay for RD, WR(L/H) Output valid delay for BHE, ALE Address output valid delay for A23 ... A0 Address output valid delay for AD15 ... AD0 (MUX mode) ...
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CLKOUT t 11 ALE A23-A16, BHE, CSx RD WR(L/H) t AD15-AD0 (read) t AD15-AD0 (write) Figure 23 Multiplexed Bus Cycle Data Sheet High Address ...
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AB CLKOUT t 11 ALE A23-A0, BHE, CSx RD WR(L/H) D15-D0 (read) D15-D0 (write) Figure 24 Demultiplexed Bus Cycle 4.7.5.1 Bus Cycle Control with the READY Input The duration of an external bus cycle can ...
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READY signal for safe synchronization is one CLKOUT period plus the input setup time. An active READY signal can be deactivated in response to the trailing (rising) edge of the corresponding command (RD or WR). If ...
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Note: If the READY input is sampled inactive at the indicated sampling point (“Not Rdy”) a READY-controlled waitstate is inserted (tpRDY), sampling the READY input active at the indicated sampling point (“Ready”) terminates the currently running bus cycle. Note the ...
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Synchronous Serial Interface Timing The following parameters are applicable for a USIC channel operated in SSC mode. Note: These parameters are not subject to production test but verified by design and/or characterization. Note: Operating Conditions apply. Table 33 is ...
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Table 34 USIC SSC Master Mode Timing for Lower Voltage Range Parameter Slave select output SELO active to first SCLKOUT transmit edge Slave select output SELO inactive after last SCLKOUT receive edge Data output DOUT valid time Receive data input ...
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Table 35 USIC SSC Slave Mode Timing for Upper Voltage Range (cont’d) Parameter Data input DX0 hold time from clock input DX1 1) receive edge Data output DOUT valid time 1) These input timings are valid for asynchronous input signal ...
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Master Mode Timing Select Output Inactive SELOx Clock Output SCLKOUT Data Output DOUT Data Input DX0 Slave Mode Timing Select Input Inactive DX2 Clock Input DX1 Data Input DX0 Data Output DOUT Transmit Edge: with this clock edge , transmit ...
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Debug Interface Timing The debugger can communicate with the XC2764X either via the 2-pin DAP interface or via the standard JTAG interface. Debug via DAP The following parameters are applicable for communication through the DAP debug interface. Note: These ...
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Table 38 DAP Interface Timing for Lower Voltage Range Parameter 1) DAP0 clock period DAP0 high time 1) DAP0 low time DAP0 clock rise time DAP0 clock fall time DAP1 setup to DAP0 rising edge DAP1 hold after DAP0 rising ...
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DAP0 DAP1 Figure 28 DAP Timing Host to Device DAP1 Figure 29 DAP Timing Device to Host Note: The transmission timing is determined by the receiving debugger by evaluating the sync-request synchronization pattern telegram. Debug via JTAG The following parameters ...
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Table 39 JTAG Interface Timing for Upper Voltage Range (cont’d) Parameter TCK low time TCK clock rise time TCK clock fall time TDI/TMS setup to TCK rising edge TDI/TMS hold after TCK rising edge TDO valid from TCK falling edge ...
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Table 40 JTAG Interface Timing for Lower Voltage Range (cont’d) Parameter TDI/TMS hold after TCK rising edge TDO valid from TCK falling edge (propagation delay) TDO high impedance to valid output from TCK 2)1) falling edge TDO valid output to ...
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TCK TMS TDI t 9 TDO Figure 31 JTAG Timing Data Sheet XC2000 Family / Value Line Electrical Parameters 121 XC2764X MC_JTAG V1.2, 2010-04 ...
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Package and Reliability The XC2000 Family devices use the package type PG-LQFP (Plastic Green - Low Profile Quad Flat Package). The following specifications must be regarded to ensure proper integration of the XC2764X in its target environment. 5.1 Packaging ...
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Package Outlines 0.5 12 0.22 ±0.05 0. 100 1 Index Marking 1) Does not include plastic or metal protrusion of 0.25 max. per side Figure 32 PG-LQFP-100-8 (Plastic Green Thin Quad Flat Package) All dimensions ...
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Thermal Considerations When operating the XC2764X in a system, the total heat generated in the chip must be dissipated to the ambient environment to prevent overheating and the resulting thermal damage. The maximum heat that can be dissipated depends ...
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