SAF-XC161CJ-16F40F BB Infineon Technologies, SAF-XC161CJ-16F40F BB Datasheet - Page 76
![IC MCU 16BIT 128KB FLSH 144TQFP](/photos/39/69/396957/qfp144_sml.jpg)
SAF-XC161CJ-16F40F BB
Manufacturer Part Number
SAF-XC161CJ-16F40F BB
Description
IC MCU 16BIT 128KB FLSH 144TQFP
Manufacturer
Infineon Technologies
Series
XC16xr
Datasheet
1.SAF-XC161CJ-16F40F_BB.pdf
(88 pages)
Specifications of SAF-XC161CJ-16F40F BB
Core Processor
C166SV2
Core Size
16-Bit
Speed
40MHz
Connectivity
CAN, EBI/EMI, I²C, SLDM, SPI, UART/USART
Peripherals
PWM, WDT
Number Of I /o
99
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.35 V ~ 2.7 V
Data Converters
A/D 12x8/10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LFQFP
Data Bus Width
16 bit
Data Ram Size
8 KB
Interface Type
2xASC, 2xSSC, 1xSDLM, 1xI2C, J1850
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
99
Number Of Timers
9
Operating Supply Voltage
5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 12 Channel
Packages
PG-TQFP-144
Max Clock Frequency
40.0 MHz
Sram (incl. Cache)
8.0 KByte
Can Nodes
2
A / D Input Lines (incl. Fadc)
12
Program Memory
128.0 KByte
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Variable Memory Cycles
External bus cycles of the XC161 are executed in five subsequent cycle phases (AB, C,
D, E, F). The duration of each cycle phase is programmable (via the TCONCSx
registers) to adapt the external bus cycles to the respective external module (memory,
peripheral, etc.).
The duration of the access phase can optionally be controlled by the external module via
the READY handshake input.
This table provides a summary of the phases and the respective choices for their
duration.
Table 21
Bus Cycle Phase
Address setup phase, the standard duration of this
phase (1 … 2 TCP) can be extended by 0 … 3 TCP
if the address window is changed
Command delay phase
Write Data setup/MUX Tristate phase
Access phase
Address/Write Data hold phase
Note: The bandwidth of a parameter (minimum and maximum value) covers the whole
Data Sheet
operating range (temperature, voltage) as well as process variations. Within a
given device, however, this bandwidth is smaller than the specified range. This is
also due to interdependencies between certain parameters. Some of these
interdependencies are described in additional notes (see standard timing).
Programmable Bus Cycle Phases (see timing diagrams)
74
Parameter Valid Values Unit
tp
tp
tp
tp
tp
AB
C
D
E
F
Electrical Parameters
1 … 2 (5)
0 … 3
0 … 1
1 … 32
0 … 3
XC161CJ-16F
Derivatives
V2.4, 2006-08
TCP
TCP
TCP
TCP
TCP