PIC18C658/CL Microchip Technology, PIC18C658/CL Datasheet - Page 251
![no-image](/images/manufacturer_photos/0/4/439/microchip_technology_sml.jpg)
PIC18C658/CL
Manufacturer Part Number
PIC18C658/CL
Description
IC MCU OTP 16KX16 CAN 68-PLCC
Manufacturer
Microchip Technology
Series
PIC® 18Cr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16C770-ISO.pdf
(8 pages)
3.PIC18C658-IPT.pdf
(366 pages)
4.PIC18C658-IPT.pdf
(16 pages)
5.PIC18C658-IPT.pdf
(16 pages)
6.PIC18C658-IPT.pdf
(16 pages)
Specifications of PIC18C658/CL
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
52
Program Memory Size
32KB (16K x 16)
Program Memory Type
OTP
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
68-PLCC
For Use With
AC164308 - MODULE SKT FOR PM3 68PLCCDVA18PQ640 - DEVICE ADAPT PIC18C658 64-TQFP
Lead Free Status / RoHS Status
Request inventory verification / Request inventory verification
Eeprom Size
-
Other names
Q1068347
- PIC16F616T-ISL PDF datasheet
- PIC16C770-ISO PDF datasheet #2
- PIC18C658-IPT PDF datasheet #3
- PIC18C658-IPT PDF datasheet #4
- PIC18C658-IPT PDF datasheet #5
- PIC18C658-IPT PDF datasheet #6
- Current page: 251 of 366
- Download datasheet (7Mb)
22.0
There are several features intended to maximize sys-
tem reliability, minimize cost through elimination of
external components, provide power saving operating
modes and offer code protection:
• OSC Selection
• RESET
• Interrupts
• Watchdog Timer (WDT)
• SLEEP
• Code Protection
• ID Locations
• In-circuit Serial Programming
PIC18CXX8 devices have a Watchdog Timer, which is
permanently enabled via the configuration bits or it can
be software-controlled. It runs off its own RC oscillator
for added reliability. There are two timers that offer nec-
essary delays on power-up. One is the Oscillator
Start-up Timer (OST), intended to keep the chip in
RESET until the crystal oscillator is stable. The other is
the Power-up Timer (PWRT), which provides a fixed
delay on power-up only, designed to keep the part in
RESET while the power supply stabilizes. With these
two timers on-chip, most applications need no external
RESET circuitry.
TABLE 22-1:
300000h
300001h
300002h
300003h
300006h
3FFFFEh DEVID1
3FFFFFh DEVID2
Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition, r = reserved.
- Power-on Reset (POR)
- Power-up Timer (PWRT)
- Oscillator Start-up Timer (OST)
- Programmable Brown-out Reset (BOR)
2000 Microchip Technology Inc.
Filename
SPECIAL FEATURES OF THE
CPU
Grayed cells are unimplemented, read as ’0’.
CONFIG1L
CONFIG1H
CONFIG2L
CONFIG2H
CONFIG4L
CONFIGURATION BITS AND DEVICE ID’S
DEV10
DEV2
Bit 7
CP
—
—
—
r
DEV1
DEV9
Bit 6
CP
—
—
—
r
OSCSEN
Advanced Information
DEV0
DEV8
Bit 5
CP
—
—
—
REV4
DEV7
Bit 4
CP
—
—
—
—
WDTPS2
BORV1
REV3
DEV6
Bit 3
SLEEP mode is designed to offer a very low current
Power-down mode. The user can wake-up from
SLEEP through external RESET, Watchdog Timer
Wake-up or through an interrupt. Several oscillator
options are also made available to allow the part to fit
the application. The RC oscillator option saves system
cost, while the LP crystal option saves power. A set of
configuration bits are used to select various options.
22.1
The configuration bits can be programmed (read as '0'),
or left unprogrammed (read as '1'), to select various
device configurations. These bits are mapped starting
at program memory location 300000h.
The user will note that address 300000h is beyond the
user program memory space. In fact, it belongs to the
configuration memory space (300000h - 3FFFFFh),
which can only be accessed using table reads and
table writes.
CP
—
—
WDTPS1
Configuration Bits
BORV0
FOSC2
REV2
DEV5
Bit 2
CP
—
WDTPS0
BODEN
FOSC1
REV1
DEV4
Bit 1
CP
r
PIC18CXX8
PWRTEN
STVREN
WDTEN
FOSC0
REV0
DEV3
Bit 0
CP
DS30475A-page 251
Unprogrammed
1111 1111
111- -111
---- 1111
---- 1111
---- --11
1111 1111
1111 1111
Default/
Value
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