PIC18C658/CL Microchip Technology, PIC18C658/CL Datasheet - Page 284
![no-image](/images/manufacturer_photos/0/4/439/microchip_technology_sml.jpg)
PIC18C658/CL
Manufacturer Part Number
PIC18C658/CL
Description
IC MCU OTP 16KX16 CAN 68-PLCC
Manufacturer
Microchip Technology
Series
PIC® 18Cr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16C770-ISO.pdf
(8 pages)
3.PIC18C658-IPT.pdf
(366 pages)
4.PIC18C658-IPT.pdf
(16 pages)
5.PIC18C658-IPT.pdf
(16 pages)
6.PIC18C658-IPT.pdf
(16 pages)
Specifications of PIC18C658/CL
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
52
Program Memory Size
32KB (16K x 16)
Program Memory Type
OTP
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
68-PLCC
For Use With
AC164308 - MODULE SKT FOR PM3 68PLCCDVA18PQ640 - DEVICE ADAPT PIC18C658 64-TQFP
Lead Free Status / RoHS Status
Request inventory verification / Request inventory verification
Eeprom Size
-
Other names
Q1068347
- PIC16F616T-ISL PDF datasheet
- PIC16C770-ISO PDF datasheet #2
- PIC18C658-IPT PDF datasheet #3
- PIC18C658-IPT PDF datasheet #4
- PIC18C658-IPT PDF datasheet #5
- PIC18C658-IPT PDF datasheet #6
- Current page: 284 of 366
- Download datasheet (7Mb)
PIC18CXX8
IORLW
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
Example:
DS30475A-page 284
Before Instruction
After Instruction
Decode
WREG
N
Z
WREG
N
Z
Q1
=
=
=
=
=
=
Inclusive OR literal with WREG
[ label ]
0
(WREG) .OR. k
N,Z
The contents of WREG are OR’ed
with the eight bit literal 'k'. The
result is placed in WREG.
1
1
literal ’k’
IORLW
Read
0000
Q2
0x9A
?
?
0xBF
1
0
k
255
IORLW k
1001
0x35
Process
Data
Q3
WREG
kkkk
Advanced Information
Write to W
Q4
kkkk
IORWF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
Example:
Before Instruction
After Instruction
Decode
RESULT =
WREG
N
Z
RESULT =
WREG
N
Z
Q1
=
=
=
=
=
=
register ’f’
Inclusive OR WREG with f
[ label ]
0
d
a
(WREG) .OR. (f)
N,Z
Inclusive OR W with register 'f'. If 'd'
is 0, the result is placed in WREG.
If 'd' is 1, the result is placed back
in register 'f' (default). If ’a’ is 0, the
Access Bank will be selected, over-
riding the BSR value. If ’a’ is 1, the
Bank will be selected as per the
BSR value.
1
1
IORWF
Read
0001
Q2
0x13
0x91
?
?
0x13
0x93
1
0
f
[0,1]
[0,1]
2000 Microchip Technology Inc.
255
RESULT, W
IORWF
00da
Process
Data
Q3
ffff
f [ ,d [,a] ]
dest
destination
Write to
Q4
ffff
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