PIC18C658/CL Microchip Technology, PIC18C658/CL Datasheet - Page 303

• Manufacturer Part Number: PIC18C658/CL
• Description: IC MCU OTP 16KX16 CAN 68-PLCC
• Manufacturer: Microchip Technology
• Series: PIC® 18Cr

Specifications of PIC18C658/CL

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 52
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: OTP
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 68-PLCC
• For Use With: AC164308 - MODULE SKT FOR PM3 68PLCCDVA18PQ640 - DEVICE ADAPT PIC18C658 64-TQFP
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Eeprom Size: -
• Other names: Q1068347

TSTFSZ
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
If skip:
If skip and followed by 2-word instruction:
Example:
2000 Microchip Technology Inc.
Before Instruction
After Instruction
operation
operation
operation
Decode
No
No
No
PC
If CNT
If CNT
Q1
Q1
Q1
PC
PC
register ’f’
operation
operation
operation
Test f, skip if 0
[ label ] TSTFSZ f [,a]
0
a
skip if f = 0
None
If ’f’ = 0, the next instruction,
fetched during the current instruc-
tion execution, is discarded and a
NOP is executed making this a two-
cycle instruction. If ’a’ is 0, the
Access Bank will be selected, over-
riding the BSR value. If ’a’ is 1, the
Bank will be selected as per the
BSR value.
1
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction
HERE
NZERO
ZERO
Read
0110
No
No
No
Q2
Q2
Q2
=
=
=
=
f
[0,1]
255
Address (HERE)
0x00,
Address (ZERO)
0x00,
Address (NZERO)
TSTFSZ
:
:
011a
operation
operation
operation
Process
Data
No
No
No
Q3
Q3
Q3
CNT
ffff
Advanced Information
operation
operation
operation
operation
No
No
No
No
Q4
Q4
Q4
ffff
XORLW
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
Example:
Before Instruction
After Instruction
Q1
Decode
WREG
N
Z
WREG
N
Z
Q2
=
=
=
=
=
=
literal ’k’
Exclusive OR literal with WREG
[ label ] XORLW k
0
(WREG) .XOR. k
N,Z
The contents of WREG are
XOR’ed with the 8-bit literal 'k'.
The result is placed in WREG.
1
1
XORLW 0xAF
Read
0000
0xB5
?
?
0x1A
0
0
k
PIC18CXX8
255
Q3
1010
Process
Data
DS30475A-page 303
kkkk
WREG
Q4
Write to
WREG
kkkk