PIC18C658/CL Microchip Technology, PIC18C658/CL Datasheet - Page 267
![no-image](/images/manufacturer_photos/0/4/439/microchip_technology_sml.jpg)
PIC18C658/CL
Manufacturer Part Number
PIC18C658/CL
Description
IC MCU OTP 16KX16 CAN 68-PLCC
Manufacturer
Microchip Technology
Series
PIC® 18Cr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16C770-ISO.pdf
(8 pages)
3.PIC18C658-IPT.pdf
(366 pages)
4.PIC18C658-IPT.pdf
(16 pages)
5.PIC18C658-IPT.pdf
(16 pages)
6.PIC18C658-IPT.pdf
(16 pages)
Specifications of PIC18C658/CL
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
52
Program Memory Size
32KB (16K x 16)
Program Memory Type
OTP
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
68-PLCC
For Use With
AC164308 - MODULE SKT FOR PM3 68PLCCDVA18PQ640 - DEVICE ADAPT PIC18C658 64-TQFP
Lead Free Status / RoHS Status
Request inventory verification / Request inventory verification
Eeprom Size
-
Other names
Q1068347
- PIC16F616T-ISL PDF datasheet
- PIC16C770-ISO PDF datasheet #2
- PIC18C658-IPT PDF datasheet #3
- PIC18C658-IPT PDF datasheet #4
- PIC18C658-IPT PDF datasheet #5
- PIC18C658-IPT PDF datasheet #6
- Current page: 267 of 366
- Download datasheet (7Mb)
23.1
ADDLW
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
Example:
2000 Microchip Technology Inc.
Before Instruction
After Instruction
Decode
Instruction Set
WREG
N
OV
C
DC
Z
WREG
N
OV
C
DC
Z
Q1
=
=
=
=
=
=
=
=
=
=
=
=
ADD literal to W
[ label ] ADDLW
0
(WREG) + k
N,OV, C, DC, Z
The contents of WREG are added
to the 8-bit literal ’k’ and the result is
placed in WREG.
1
1
ADDLW
literal ’k’
Read
0000
Q2
0x10
?
?
?
?
?
0x25
0
0
0
0
0
k
255
0x15
1111
Process
Data
Q3
WREG
k
kkkk
Advanced Information
Write to W
Q4
kkkk
ADDWF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
Example:
Before Instruction
After Instruction
Decode
WREG
REG
N
OV
C
DC
Z
WREG
REG
N
OV
C
DC
Z
Q1
=
=
=
=
=
=
=
=
=
=
=
=
=
=
register ’f’
ADD W to f
[ label ] ADDWF
0
d
a
(WREG) + (f)
N,OV, C, DC, Z
Add WREG to register ’f’. If ’d’ is 0,
the result is stored in WREG. If ’d’
is 1, the result is stored back in reg-
ister 'f' (default). If ’a’ is 0, the
Access Bank will be selected. If ’a’
is 1, the Bank will be selected as
per the BSR value.
1
1
ADDWF
Read
0010
Q2
0x17
0xC2
?
?
?
?
?
0xD9
0xC2
1
0
0
0
0
f
[0,1]
[0,1]
PIC18CXX8
255
01da
REG, W
Process
Data
Q3
DS30475A-page 267
dest
f [,d] [,a]
ffff
destination
Write to
Q4
ffff
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