PIC18C658/CL Microchip Technology, PIC18C658/CL Datasheet - Page 95
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PIC18C658/CL
Manufacturer Part Number
PIC18C658/CL
Description
IC MCU OTP 16KX16 CAN 68-PLCC
Manufacturer
Microchip Technology
Series
PIC® 18Cr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16C770-ISO.pdf
(8 pages)
3.PIC18C658-IPT.pdf
(366 pages)
4.PIC18C658-IPT.pdf
(16 pages)
5.PIC18C658-IPT.pdf
(16 pages)
6.PIC18C658-IPT.pdf
(16 pages)
Specifications of PIC18C658/CL
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
52
Program Memory Size
32KB (16K x 16)
Program Memory Type
OTP
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
68-PLCC
For Use With
AC164308 - MODULE SKT FOR PM3 68PLCCDVA18PQ640 - DEVICE ADAPT PIC18C658 64-TQFP
Lead Free Status / RoHS Status
Request inventory verification / Request inventory verification
Eeprom Size
-
Other names
Q1068347
- PIC16F616T-ISL PDF datasheet
- PIC16C770-ISO PDF datasheet #2
- PIC18C658-IPT PDF datasheet #3
- PIC18C658-IPT PDF datasheet #4
- PIC18C658-IPT PDF datasheet #5
- PIC18C658-IPT PDF datasheet #6
- Current page: 95 of 366
- Download datasheet (7Mb)
8.4
PORTD is an 8-bit wide, bi-directional port. The corre-
sponding Data Direction register is TRISD. Setting a
TRISD bit (=1) will make the corresponding PORTD pin
an input (i.e., put the corresponding output driver in a
hi-impedance mode). Clearing a TRISD bit (=0) will
make the corresponding PORTD pin an output (i.e., put
the contents of the output latch on the selected pin).
Read-modify-write operations on the LATD register
reads and writes the latched output value for PORTD.
PORTD is an 8-bit port with Schmitt Trigger input buff-
ers. Each pin is individually configurable as an input or
output.
PORTD can be configured as an 8-bit wide micro-
processor port (parallel slave port), by setting control
bit PSPMODE (PSPCON register). In this mode, the
input buffers are TTL. See Section 9.0 for additional
information on the Parallel Slave Port (PSP).
EXAMPLE 8-4:
2000 Microchip Technology Inc.
CLRF
CLRF
MOVLW
MOVWF
PORTD, TRISD and LATD Registers
PORTD
LATD
0xCF
TRISD
INITIALIZING PORTD
; Initialize PORTD by
; clearing output
; data latches
; Alternate method
; to clear output
; data latches
; Value used to
; initialize data
; direction
; Set RD3:RD0 as inputs
; RD5:RD4 as outputs
; RD7:RD6 as inputs
Advanced Information
FIGURE 8-7:
WR TRISD
WR LATD
or
WR PORTD
Note: I/O pins have diode protection to V
Data
Bus
RD PORTD
TRIS Latch
Data Latch
D
D
CK
CK
PORTD BLOCK DIAGRAM
IN I/O PORT MODE
RD LATD
RD TRISD
Q
Q
PIC18CXX8
Q
EN
EN
DD
D
DS30475A-page 95
Schmitt
Trigger
Input
Buffer
and V
SS
.
I/O Pin
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