ATMEGA161-8PI Atmel, ATMEGA161-8PI Datasheet - Page 12

• Manufacturer Part Number: ATMEGA161-8PI
• Description: IC AVR MCU 16K 8MHZ IND 40-DIP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA161-8PI

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Data Converters: -
• Other names: ATMEGA1618PI

SRAM Data Memory
12
ATmega161(L)
Figure 8 shows how the ATmega161 SRAM memory is organized.
Figure 8. SRAM Organization
The lower 1120 Data memory locations address the Register File, the I/O memory and
the internal data SRAM. The first 96 locations address the Register File and I/O memory
and the next 1K locations address the internal data SRAM. An optional external Data
memory device can be placed in the same SRAM memory space. This memory device
will occupy the locations following the internal SRAM and up to as much as 64K - 1,
depending on external memory size.
When the addresses accessing the Data memory space exceed the internal data SRAM
locations, the memory device is accessed using the same instructions as for the internal
data SRAM access. When the internal data space is accessed, the read and write
strobe pins (RD and WR) are inactive during the whole access cycle. External memory
operation is enabled by setting the SRE bit in the MCUCR Register. See “Interface to
External Memory” on page 84 for details.
Accessing external memory takes one additional clock cycle per byte compared to
access of the internal SRAM. This means that the commands LD, ST, LDS, STS,
PUSH, and POP take one additional clock cycle. If the Stack is placed in external mem-
ory, interrupts, subroutine calls and returns take two clock cycles extra because the 2-
byte Program Counter is pushed and popped. When external memory interface is used
with wait state, two additional clock cycles are used per byte. This has the following
effect: Data transfer instructions take two extra clock cycles, whereas interrupt, subrou-
tine calls and returns will need four clock cycles more than specified in the Instruction
Set manual.
I/O Registers
Register File
R29
R30
R31
$3D
$3E
$00
$01
$02
$3F
R0
R1
R2
…
…
Data Address Space
Internal SRAM
$001D
$001E
$001F
$005D
$005E
$005F
$045E
$045F
$0000
$0001
$0002
$0020
$0021
$0022
$0060
$0061
…
…
…
1228D–AVR–02/07