ATMEGA161-8PI Atmel, ATMEGA161-8PI Datasheet - Page 67

• Manufacturer Part Number: ATMEGA161-8PI
• Description: IC AVR MCU 16K 8MHZ IND 40-DIP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA161-8PI

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Data Converters: -
• Other names: ATMEGA1618PI

SPI Status Register – SPSR
1228D–AVR–02/07
• Bits 1, 0
These two bits control the SCK rate of the device configured as a Master. SPR1 and
SPR0 have no effect on the Slave. The relationship between SCK and the Oscillator
Clock frequency (f
Table 23. Relationship between SCK and the Oscillator Frequency
Note:
• Bit 7
When a serial transfer is complete, the SPIF bit is set (one) and an interrupt is gener-
ated if SPIE in SPCR is set (one) and global interrupts are enabled. If SS is an input and
is driven low when the SPI is in Master mode, this will also set the SPIF Flag. SPIF is
cleared by hardware when executing the corresponding Interrupt Handling Vector. Alter-
natively, the SPIF bit is cleared by first reading the SPI Status Register with SPIF set
(one), then by accessing the SPI Data Register (SPDR).
• Bit 6
The WCOL bit is set if the SPI Data Register (SPDR) is written during a data transfer.
The WCOL bit (and the SPIF bit) are cleared (zero) by first reading the SPI Status Reg-
ister with WCOL set (one), and then by accessing the SPI Data Register.
• Bits 5..1
These bits are reserved bits in the ATmega161 and will always read as zero.
• Bit 0
When this bit is set (one), the SPI speed (SCK frequency) will be doubled when the SPI
is in Master mode (see Table 23). This means that the maximum SCK period will be two
CPU clock periods. When the SPI is configured as Slave, the SPI is only guaranteed to
work at f
The SPI interface on the ATmega161 is also used for Program memory and EEPROM
downloading or uploading. See page 125 for serial programming and verification.
Bit
$0E ($2E)
Read/Write
Initial Value
SPI2X
–
–
–
1. When the SPI is configured as Slave, the SPI is only guaranteed to work at
0
0
0
0
1
1
1
1
cl
SPIF: SPI Interrupt Flag
WCOL: Write Collision Flag
SPI2X: Double SPI Speed Bit
/4.
–
–
SPR1, SPR0: SPI Clock Rate Select 1 and 0
Res: Reserved Bits
SPIF
R
7
0
cl
) is shown in Table 23:
WCOL
SPR1
R
6
0
0
0
1
1
0
0
1
1
R
5
–
0
SPR0
R
4
–
0
0
1
0
1
0
1
0
1
R
3
–
0
R
2
–
0
ATmega161(L)
SCK Frequency
R
1
–
0
f
(1)
f
f
f
f
cl
f
f
f
cl
cl
cl
cl
cl
/128
cl
cl
/16
/64
/32
/64
/4
/2
/8
SPI2X
R/W
0
0
f
cl
/4.
SPSR
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