ATMEGA161-8PI Atmel, ATMEGA161-8PI Datasheet - Page 33

• Manufacturer Part Number: ATMEGA161-8PI
• Description: IC AVR MCU 16K 8MHZ IND 40-DIP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA161-8PI

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Data Converters: -
• Other names: ATMEGA1618PI

Timer/Counter Interrupt Flag
Register – TIFR
1228D–AVR–02/07
• Bit 7
The TOV1 is set (one) when an overflow occurs in Timer/Counter1. TOV1 is cleared by
hardware when executing the corresponding Interrupt Handling Vector. Alternatively,
TOV1 is cleared by writing a logical “1” to the Flag. When the I-bit in SREG, and TOIE1
(Timer/Counter1 Overflow Interrupt Enable), and TOV1 are set (one), the
Timer/Counter1 Overflow Interrupt is executed. In PWM mode, this bit is set when
Timer/Counter1 changes counting direction at $0000.
• Bit 6
The OCF1A bit is set (one) when a compare match occurs between the Timer/Counter1
and the data in OCR1A (Output Compare Register 1A). OCF1A is cleared by hardware
when executing the corresponding Interrupt Handling Vector. Alternatively, OCF1A is
cleared by writing a logical “1” to the Flag. When the I-bit in SREG and OCIE1A
(Timer/Counter1 Compare Match Interrupt A Enable) and OCF1A are set (one), the
Timer/Counter1 Compare A Match Interrupt is executed.
• Bit 5
The OCF1B bit is set (one) when a compare match occurs between the Timer/Counter1
and the data in OCR1B (Output Compare Register 1B). OCF1B is cleared by hardware
when executing the corresponding Interrupt Handling Vector. Alternatively, OCF1B is
cleared by writing a logical “1” to the Flag. When the I-bit in SREG and OCIE1B
(Timer/Counter1 Compare Match Interrupt B Enable) and OCF1B are set (one), the
Timer/Counter1 Compare B Match Interrupt is executed.
• Bit 4
The bit TOV2 is set (one) when an overflow occurs in Timer/Counter2. TOV2 is cleared
by hardware when executing the corresponding Interrupt Handling Vector. Alternatively,
TOV2 is cleared by writing a logical “1” to the Flag. When the SREG I-bit and TOIE2
(Tim er/Co un ter2 Ove rflow Inte rrup t En able) an d TO V2 a re set (o ne) , th e
Timer/Counter2 Overflow interrupt is executed.
• Bit 3
The ICF1 bit is set (one) to flag an Input Capture Event, indicating that the
Timer/Counter1 value has been transferred to the Input Capture Register (ICR1). ICF1
is cleared by hardware when executing the corresponding Interrupt Handling Vector.
Alternatively, ICF1 is cleared by writing a logical “1” to the Flag. When the SREG I-bit
and TICIE1 (Timer/Counter1 Input Capture Interrupt Enable) and ICF1 are set (one), the
Timer/Counter1 Capture Interrupt is executed.
• Bit 2
The OCF2 bit is set (one) when a Compare Match occurs between the Timer/Counter2
and the data in OCR2 (Output Compare Register 2). OCF2 is cleared by hardware when
executing the corresponding Interrupt Handling Vector. Alternatively, OCF2 is cleared
by writing a logical “1” to the Flag. When the I-bit in SREG and OCIE2 (Timer/Counter2
Bit
$38 ($58)
Read/Write
Initial Value
–
–
–
–
–
–
TOV1: Timer/Counter1 Overflow Flag
OCF1A: Output Compare Flag 1A
OCF1B: Output Compare Flag 1B
TOV2: Timer/Counter2 Overflow Flag
ICF1: Input Capture Flag 1
OCF2: Output Compare Flag 2
TOV1
R/W
7
0
OCF1A
R/W
6
0
OCIFB
R/W
5
0
TOV2
R/W
4
0
ICF1
R/W
3
0
OCF2
R/W
2
0
ATmega161(L)
TOV0
R/W
1
0
OCF0
R/W
0
0
TIFR
33