ATMEGA161-8PI Atmel, ATMEGA161-8PI Datasheet - Page 36

• Manufacturer Part Number: ATMEGA161-8PI
• Description: IC AVR MCU 16K 8MHZ IND 40-DIP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA161-8PI

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Data Converters: -
• Other names: ATMEGA1618PI

Extended MCU Control
Register – EMCUCR
Sleep Modes
Idle Mode
36
ATmega161(L)
The Extended MCU Control Register contains control bits for External Interrupt 2, Sleep
mode bit and control bits for the external memory interface.
• Bit 7
When this bit is set (one) and Sleep mode bit 1 (SM1) in MCUCR is set, Power-save
mode is selected as Sleep mode. Refer to page 36 for a detailed description of the
Sleep modes.
• Bits 6..4
It is possible to configure different wait states for different external memory addresses in
ATmega161. The SRL2 - SRL0 bits are used to define at which address the different
wait states will be configured. See “Interface to External Memory” on page 84 for a
detailed description.
• Bits 3..1
The SRW01, SRW00 and SRW11 bits are used to set up extra wait states in the exter-
nal memory interface. See “Interface to External Memory” on page 84 for a detailed
description.
• Bit 0
The external interrupt 2 is activated by the external pin INT2 if the SREG I-Flag and the
corresponding interrupt mask in the GIMSK are set. If ISC2 is cleared (zero), a falling
edge on INT2 activates the interrupt. If ISC2 is set (one), a rising edge on INT2 activates
the interrupt. Edges on INT2 are registered asynchronously. Pulses on INT2 wider than
50 ns will generate an interrupt. Shorter pulses are not guaranteed to generate an
interrupt.
When changing the ISC2 bit, an interrupt can occur. Therefore, it is recommended to
first disable INT2 by clearing its Interrupt Enable bit in the GIMSK Register. Then, ISC2
bit can be changed. Finally, the INT2 Interrupt Flag should be cleared by writing a logical
“1” to its Interrupt Flag bit in the GIFR Register before the interrupt is re-enabled.
To enter any of the three Sleep modes, the SE bit in MCUCR must be set (one) and a
SLEEP instruction must be executed. The SM1 bit in the MCUCR Register and SM0 bit
in the EMCUCR Register select which Sleep mode (Idle, Power-down or Power-save)
will be activated by the SLEEP instruction (see Table 6). If an enabled interrupt occurs
while the MCU is in a Sleep mode, the MCU awakes. The CPU is then halted for four
cycles, it executes the interrupt routine, and resumes execution from the instruction fol-
lowing SLEEP. The contents of the Register File, SRAM and I/O memory are unaltered.
If a reset occurs during Sleep mode, the MCU wakes up and executes from the Reset
Vector.
When the SM1/SM0 bits are set to 00, the SLEEP instruction makes the MCU enter the
Idle mode, stopping the CPU but allowing SPI, UARTs, Analog Comparator,
Timer/Counters, Watchdog, and the Interrupt System to continue operating. This
enables the MCU to wake up from external triggered interrupts as well as internal ones
like the Timer Overflow and UART Receive Complete interrupts. If wake-up from the
Bit
$36 ($56)
Read/Write
Initial Value
–
–
SM0: Sleep Mode Bit 0
ISC2: Interrupt Sense Control 2
–
–
SRL2, SRL1, SRL0: External SRAM Limit
SRW01, SRW00, SRW11: External SRAM Wait State Select Bits
SM0
R/W
7
0
SRL2
R/W
6
0
SRL1
R/W
5
0
SRL0
R/W
4
0
SRW01
R/W
3
0
SRW00
R/W
2
0
SRW11
R/W
1
0
ISC2
R/W
0
0
1228D–AVR–02/07
EMCUCR