ATMEGA161-8PI Atmel, ATMEGA161-8PI Datasheet - Page 31

• Manufacturer Part Number: ATMEGA161-8PI
• Description: IC AVR MCU 16K 8MHZ IND 40-DIP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA161-8PI

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Data Converters: -
• Other names: ATMEGA1618PI

General Interrupt Flag
Register – GIFR
Timer/Counter Interrupt Mask
Register – TIMSK
1228D–AVR–02/07
• Bits 4..0
These bits are reserved bits in the ATmega161 and always read as zero.
• Bit 7
When an event on the INT1 pin triggers an interrupt request, INTF1 becomes set (one).
If the I-bit in SREG and the INT1 bit in GIMSK are set (one), the MCU will jump to the
Interrupt Vector at address $004. The Flag is cleared when the interrupt routine is exe-
cuted. Alternatively, the Flag can be cleared by writing a logical “1” to it.
• Bit 6
When an event on the INT0 pin triggers an interrupt request, INTF0 becomes set (one).
If the I-bit in SREG and the INT0 bit in GIMSK are set (one), the MCU will jump to the
Interrupt Vector at address $002. The Flag is cleared when the interrupt routine is exe-
cuted. Alternatively, the Flag can be cleared by writing a logical “1” to it.
• Bit 5
When an event on the INT2 pin triggers an interrupt request, INTF2 becomes set (one).
If the I-bit in SREG and the INT2 bit in GIMSK are set (one), the MCU will jump to the
Interrupt Vector at address $006. The Flag is cleared when the interrupt routine is exe-
cuted. Alternatively, the Flag can be cleared by writing a logical “1” to it.
• Bits 4..0
These bits are reserved bits in the ATmega161 and always read as zero.
• Bit 7
When the TOIE1 bit is set (one) and the I-bit in the Status Register is set (one), the
Timer/Counter1 Overflow interrupt is enabled. The corresponding interrupt (at Vector
$012) is executed if an overflow in Timer/Counter1 occurs, i.e., when the TOV1 bit is set
in the Timer/Counter Interrupt Flag Register (TIFR).
• Bit 6
When the OCIE1A bit is set (one) and the I-bit in the Status Register is set (one), the
Timer/Counter1 CompareA Match interrupt is enabled. The corresponding interrupt (at
Vector $00e) is executed if a Compare A Match in Timer/Counter1 occurs, i.e., when the
OCF1A bit is set in the Timer/Counter Interrupt Flag Register (TIFR).
Bit
$3A ($5A)
Read/Write
Initial Value
Bit
$39 ($59)
Read/Write
Initial Value
–
–
–
–
–
INTF1: External Interrupt Flag1
INTF0: External Interrupt Flag0
INTF2: External Interrupt Flag2
TOIE1: Timer/Counter1 Overflow Interrupt Enable
OCE1A: Timer/Counter1 Output CompareA Match Interrupt Enable
–
–
Res: Reserved Bits
Res: Reserved Bits
TOIE1
INTF1
R/W
R/W
7
0
7
0
OCIE1A
INTF0
R/W
R/W
6
0
6
0
OCIE1B
INTF2
R/W
R/W
5
0
5
0
TOIE2
R/W
R
4
0
4
–
0
TICIE1
R/W
R
3
0
3
–
0
OCIE2
R/W
R
2
–
0
2
0
ATmega161(L)
TOIE0
R/W
R
1
–
0
1
0
OCIE0
R/W
R
0
–
0
0
0
TIMSK
GIFR
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