ATMEGA161-8PI Atmel, ATMEGA161-8PI Datasheet - Page 29
![IC AVR MCU 16K 8MHZ IND 40-DIP](/photos/6/70/67049/453-40-dip_sml.jpg)
ATMEGA161-8PI
Manufacturer Part Number
ATMEGA161-8PI
Description
IC AVR MCU 16K 8MHZ IND 40-DIP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheet
1.ATMEGA161-8AC.pdf
(159 pages)
Specifications of ATMEGA161-8PI
Core Processor
AVR
Core Size
8-Bit
Speed
8MHz
Connectivity
SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
35
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
40-DIP (0.600", 15.24mm)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Data Converters
-
Other names
ATMEGA1618PI
- Current page: 29 of 159
- Download datasheet (2Mb)
MCU Status Register –
MCUSR
Interrupt Handling
1228D–AVR–02/07
The MCU Status Register provides information on which reset source caused an MCU
Reset.
• Bits 7..4
These bits are reserved bits in the ATmega161 and always read as zero.
• Bit 3
This bit is set if a Watchdog Reset occurs. The bit is cleared by a Power-on Reset or by
writing a logical “0” to the Flag.
• Bit 2
This bit are reserved bit in the ATmega161 and always read as zero.
• Bit 1
This bit is set if an External Reset occurs. The bit is cleared by a Power-on Reset or by
writing a logical “0” to the Flag.
• Bit 0
This bit is set if a Power-on Reset occurs. The bit is cleared only by writing a logical “0”
to the Flag.
To make use of the Reset Flags to identify a reset condition, the user should read and
then clear the MCUSR as early as possible in the program. If the register is cleared
before another reset occurs, the source of the reset can be found by examining the
Reset Flags.
The ATmega161 has two 8-bit Interrupt Mask Control Registers; GIMSK (General Inter-
rupt Mask Register) and TIMSK (Timer/Counter Interrupt Mask Register).
When an interrupt occurs, the Global Interrupt Enable I-bit is cleared (zero) and all inter-
rupts are disabled. The user software can set (one) the I-bit to enable nested interrupts.
The I-bit is set (one) when a Return from Interrupt instruction (RETI) is executed.
When the Program Counter is vectored to the actual Interrupt Vector in order to execute
the interrupt handling routine, hardware clears the corresponding flag that generated the
interrupt. Some of the Interrupt Flags can also be cleared by writing a logical “1” to the
Flag bit position(s) to be cleared.
If an interrupt condition occurs when the corresponding interrupt enable bit is cleared
(zero), the Interrupt Flag will be set and remembered until the interrupt is enabled or the
Flag is cleared by software.
If one or more interrupt conditions occur when the global interrupt enable bit is cleared
(zero), the corresponding Interrupt Flag(s) will be set and remembered until the global
interrupt enable bit is set (one), and will be executed by order of priority.
Note that external level interrupt does not have a flag and will only be remembered for
as long as the interrupt condition is present.
Bit
$34 ($54)
Read/Write
Initial Value
–
–
–
–
WDRF: Watchdog Reset Flag
Res: Reserved Bit
EXTRF: External Reset Flag
PORF: Power-on Reset Flag
–
Res: Reserved Bits
R
7
–
0
R
6
–
0
R
5
–
0
R
4
–
0
WDRF
R/W
3
R
2
–
ATmega161(L)
See Bit Description
EXTRF
R/W
1
PORF
R/W
0
MCUSR
29
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