AT90CAN128-16MJ Atmel, AT90CAN128-16MJ Datasheet - Page 215
![IC MCU AVR FLASH 128K 64-QFN](/photos/12/13/121326/313-64-qfn_sml.jpg)
AT90CAN128-16MJ
Manufacturer Part Number
AT90CAN128-16MJ
Description
IC MCU AVR FLASH 128K 64-QFN
Manufacturer
Atmel
Series
AVR® 90CANr
Specifications of AT90CAN128-16MJ
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
CAN, EBI/EMI, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-VQFN Exposed Pad, 64-HVQFN, 64-SQFN, 64-DHVQFN
For Use With
ATDVK90CAN1 - KIT DEV FOR AT90CAN128 MCU
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
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18.7
Figure 18-10. Interfacing the Application to the TWI in a Typical Transmission
7679H–CAN–08/08
Hardware
TWI bus
Action
TWI
Using the TWI
1. Application
writes to TWCR
to initiate
transmission of
START.
START
2. TWINT set.
Status code indicates
START condition sent
3. Check TWSR to see if
START was sent. Application
loads SLA+W into TWDR, and
loads appropriate control signals
into TWCR, making sure that
TWINT is written to one.
TWGCE is used to enable recognition of the general call address (0x00). There is an associated
address comparator that looks for the slave address (or general call address if enabled) in the
received serial address. If a match is found, an interrupt request is generated. If set, this bit
enables the recognition of a General Call given over the TWI Serial Bus.
The AVR TWI is byte-oriented and interrupt based. Interrupts are issued after all bus events, like
reception of a byte or transmission of a START condition. Because the TWI is interrupt-based,
the application software is free to carry on other operations during a TWI byte transfer. Note that
the TWI Interrupt Enable (TWIE) bit in TWCR together with the Global Interrupt Enable bit in
SREG allow the application to decide whether or not assertion of the TWINT flag should gener-
ate an interrupt request. If the TWIE bit is cleared, the application must poll the TWINT flag in
order to detect actions on the TWI bus.
When the TWINT flag is asserted, the TWI has finished an operation and awaits application
response. In this case, the TWI Status Register (TWSR) contains a value indicating the current
state of the TWI bus. The application software can then decide how the TWI should behave in
the next TWI bus cycle by manipulating the TWCR and TWDR Registers.
Figure 18-10
this example, a master wishes to transmit a single data byte to a slave. This description is quite
abstract, a more detailed explanation follows later in this section. A simple code example imple-
menting the desired behavior is also presented.
1. The first step in a TWI transmission is to transmit a START condition. This is done by
writing a specific value into TWCR, instructing the TWI hardware to transmit a START
condition. Which value to write is described later on. However, it is important that the
TWINT bit is set in the value written. Writing a one to TWINT clears the flag. The TWI
will not start any operation as long as the TWINT bit in TWCR is set. Immediately after
SLA+W
is a simple example of how the application can interface to the TWI hardware. In
4. TWINT set.
Status code indicates
SLA+W sendt,
ACK received
A
5. Check TWSR to see if SLA+W
was sent and ACK received.
Application loads data into TWDR,
and loads appropriate control signals
into TWCR, making sure that TWINT
is written to one.
Data
6. TWINT set.
Status code indicates
data sent,
ACK received
AT90CAN32/64/128
A
7. Check TWSR to see if data
was sent and ACK received.
Application loads appropriate
control signals to send STOP
into TWCR, making sure that
TWINT is written to one.
STOP
TWINT set
Indicates
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