AT90CAN128-16MJ Atmel, AT90CAN128-16MJ Datasheet - Page 46
![IC MCU AVR FLASH 128K 64-QFN](/photos/12/13/121326/313-64-qfn_sml.jpg)
AT90CAN128-16MJ
Manufacturer Part Number
AT90CAN128-16MJ
Description
IC MCU AVR FLASH 128K 64-QFN
Manufacturer
Atmel
Series
AVR® 90CANr
Specifications of AT90CAN128-16MJ
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
CAN, EBI/EMI, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-VQFN Exposed Pad, 64-HVQFN, 64-SQFN, 64-DHVQFN
For Use With
ATDVK90CAN1 - KIT DEV FOR AT90CAN128 MCU
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
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6. Power Management and Sleep Modes
6.0.1
46
AT90CAN32/64/128
Sleep Mode Control Register – SMCR
Sleep modes enable the application to shut down unused modules in the MCU, thereby saving
power. The AVR provides various sleep modes allowing the user to tailor the power consump-
tion to the application’s requirements.
To enter any of the five sleep modes, the SE bit in SMCR must be written to logic one and a
SLEEP instruction must be executed. The SM2, SM1, and SM0 bits in the SMCR Register select
which sleep mode (Idle, ADC Noise Reduction, Power-down, Power-save, or Standby) will be
activated by the SLEEP instruction. See
while the MCU is in a sleep mode, the MCU wakes up. The MCU is then halted for four cycles in
addition to the start-up time, executes the interrupt routine, and resumes execution from the
instruction following SLEEP. The contents of the register file and SRAM are unaltered when the
device wakes up from sleep. If a reset occurs during sleep mode, the MCU wakes up and exe-
cutes from the Reset Vector.
Figure 5-1 on page 37
distribution. The figure is helpful in selecting an appropriate sleep mode.
The Sleep Mode Control Register contains control bits for power management.
• Bit 7..4 – Reserved Bits
These bits are reserved for future use.
• Bits 3..1 – SM2..0: Sleep Mode Select Bits 2, 1, and 0
These bits select between the five available sleep modes as shown in
Table 6-1.
Note:
• Bit 1 – SE: Sleep Enable
The SE bit must be written to logic one to make the MCU enter the sleep mode when the SLEEP
instruction is executed. To avoid the MCU entering the sleep mode unless it is the programmer’s
Bit
Read/Write
Initial Value
SM2
0
0
0
0
1
1
1
1
1. Standby mode is only recommended for use with external crystals or resonators.
Sleep Mode Select
R
7
–
0
SM1
0
0
1
1
0
0
1
1
presents the different clock systems in the AT90CAN32/64/128, and their
R
6
–
0
R
5
–
0
SM0
0
1
0
1
0
1
0
1
Table 6-1
R
4
–
0
Sleep Mode
Idle
ADC Noise Reduction
Power-down
Power-save
Reserved
Reserved
Standby
Reserved
SM2
R/W
3
0
for a summary. If an enabled interrupt occurs
(1)
SM1
R/W
2
0
SM0
R/W
1
0
Table
R/W
SE
0
0
6-1.
SMCR
7679H–CAN–08/08
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