AT90CAN128-16MJ Atmel, AT90CAN128-16MJ Datasheet - Page 258
![IC MCU AVR FLASH 128K 64-QFN](/photos/12/13/121326/313-64-qfn_sml.jpg)
AT90CAN128-16MJ
Manufacturer Part Number
AT90CAN128-16MJ
Description
IC MCU AVR FLASH 128K 64-QFN
Manufacturer
Atmel
Series
AVR® 90CANr
Specifications of AT90CAN128-16MJ
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
CAN, EBI/EMI, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-VQFN Exposed Pad, 64-HVQFN, 64-SQFN, 64-DHVQFN
For Use With
ATDVK90CAN1 - KIT DEV FOR AT90CAN128 MCU
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
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19.10.9
19.10.10 CAN Bit Timing Register 3 - CANBT3
258
AT90CAN32/64/128
CAN Bit Timing Register 2 - CANBT2
The period of the CAN controller system clock Tscl is programmable and determines the individ-
ual bit timing.
If BRP[5..0]=0, see
Point(s)” on page
• Bit 0 – Reserved Bit
This bit is reserved for future use. For compatibility with future devices, it must be written to zero
when CANBT1 is written.
• Bit 7– Reserved Bit
This bit is reserved for future use. For compatibility with future devices, it must be written to zero
when CANBT2 is written.
• Bit 6:5 – SJW1:0: Re-Synchronization Jump Width
To compensate for phase shifts between clock oscillators of different bus controllers, the control-
ler must re-synchronize on any relevant signal edge of the current transmission.
The synchronization jump width defines the maximum number of clock cycles. A bit period may
be shortened or lengthened by a re-synchronization.
• Bit 4 – Reserved Bit
This bit is reserved for future use. For compatibility with future devices, it must be written to zero
when CANBT2 is written.
• Bit 3:1 – PRS2:0: Propagation Time Segment
This part of the bit time is used to compensate for the physical delay times within the network. It
is twice the sum of the signal propagation time on the bus line, the input comparator delay and
the output driver delay.
• Bit 0 – Reserved Bit
This bit is reserved for future use. For compatibility with future devices, it must be written to zero
when CANBT2 is written.
Initial Value
Initial Value
Read/Write
Read/Write
Bit
Bit
7
7
-
-
-
-
-
-
259.
Section 19.4.3 ”Baud Rate” on page 242
PHS22
SJW1
R/W
R/W
6
0
6
0
PHS21
SJW0
R/W
R/W
5
0
5
0
Tprs = Tscl x (PRS [2:0] + 1)
PHS20
R/W
0
4
4
-
-
-
Tscl =
Tsjw = Tscl x (SJW [1:0] +1)
PHS12
PRS2
R/W
R/W
3
0
3
0
clk
BRP[5:0] + 1
IO
frequency
PHS11
PRS1
R/W
R/W
2
0
2
0
and
PHS10
PRS0
R/W
R/W
Section • ”Bit 0 – SMP: Sample
1
0
1
0
SMP
R/W
0
0
0
-
-
-
CANBT2
CANBT3
7679H–CAN–08/08
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