AT90CAN128-16MJ Atmel, AT90CAN128-16MJ Datasheet - Page 29
![IC MCU AVR FLASH 128K 64-QFN](/photos/12/13/121326/313-64-qfn_sml.jpg)
AT90CAN128-16MJ
Manufacturer Part Number
AT90CAN128-16MJ
Description
IC MCU AVR FLASH 128K 64-QFN
Manufacturer
Atmel
Series
AVR® 90CANr
Specifications of AT90CAN128-16MJ
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
CAN, EBI/EMI, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-VQFN Exposed Pad, 64-HVQFN, 64-SQFN, 64-DHVQFN
For Use With
ATDVK90CAN1 - KIT DEV FOR AT90CAN128 MCU
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
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4.5.3
4.5.4
4.5.5
7679H–CAN–08/08
Address Latch Requirements
Pull-up and Bus-keeper
Timing
Due to the high-speed operation of the XRAM interface, the address latch must be selected with
care for system frequencies above 8 MHz @ 4V and 4 MHz @ 2.7V. When operating at condi-
tions above these frequencies, the typical old style 74HC series latch becomes inadequate. The
External Memory Interface is designed in compliance to the 74AHC series latch. However, most
latches can be used as long they comply with the main timing parameters. The main parameters
for the address latch are:
The External Memory Interface is designed to guaranty minimum address hold time after G is
asserted low of t
tion 26.9 on page
when calculating the access time requirement of the external component. The data setup time
before G low (t
(dependent on the capacitive load).
Figure 4-5.
The pull-ups on the AD7:0 ports may be activated if the corresponding Port register is written to
one. To reduce power consumption in sleep mode, it is recommended to disable the pull-ups by
writing the Port register to zero before entering sleep.
The XMEM interface also provides a bus-keeper on the AD7:0 lines. The bus-keeper can be dis-
abled and enabled in software as described in
on page
AD7:0 bus when these lines would otherwise be tri-stated by the XMEM interface.
External Memory devices have different timing requirements. To meet these requirements, the
AT90CAN32/64/128 XMEM interface provides four different wait-states as shown in
is important to consider the timing specification of the External Memory device before selecting
the wait-state. The most important parameters are the access time for the external memory
compared to the set-up requirement of the AT90CAN32/64/128. The access time for the Exter-
nal Memory is defined to be the time from receiving the chip select/address until the data of this
• D to Q propagation delay (t
• Data setup time before G low (t
• Data (address) hold time after G low (
33. When enabled, the bus-keeper will ensure a defined logic level (zero or one) on the
External SRAM Connected to the AVR
SU
h
) must not exceed address valid to ALE low (t
= 5 ns. Refer to t
375. The D-to-Q propagation delay (t
AVR
AD7:0
A15:8
ALE
WR
PD
RD
).
SU
LAXX_LD
).
TH
/
).
t
LLAXX_ST
“External Memory Control Register B – XMCRB”
D
G
in
Q
Table 26-7
PD
AT90CAN32/64/128
) must be taken into consideration
AVLLC
through
) minus PCB wiring delay
D[7:0]
A[15:8]
A[7:0]
RD
WR
SRAM
Table 26-14
Table
of
4-4. It
Sec-
29
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