AT90CAN128-16MJ Atmel, AT90CAN128-16MJ Datasheet - Page 349

• Manufacturer Part Number: AT90CAN128-16MJ
• Description: IC MCU AVR FLASH 128K 64-QFN
• Manufacturer: Atmel
• Series: AVR® 90CANr

Specifications of AT90CAN128-16MJ

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: CAN, EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VQFN Exposed Pad, 64-HVQFN, 64-SQFN, 64-DHVQFN
• For Use With: ATDVK90CAN1 - KIT DEV FOR AT90CAN128 MCU
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

25.7.2
25.7.3
25.8
7679H–CAN–08/08
SPI Serial Programming
Pin Mapping
Parameters
Figure 25-7. Serial Programming and Verify
Notes:
When programming the EEPROM, an auto-erase cycle is built into the self-timed programming
operation (in the Serial mode ONLY) and there is no need to first execute the Chip Erase
instruction. The Chip Erase operation turns the content of every memory location in both the
Program and EEPROM arrays into 0xFF.
Depending on CKSEL Fuses, a valid clock must be present. The minimum low and high periods
for the serial clock (SCK) input are defined as follows:
Low: > 2 CPU clock cycles for f
High: > 2 CPU clock cycles for f
Table 25-13. Pin Mapping Serial Programming
The Flash parameters are given in
Table 25-12 on page
When writing serial data to the AT90CAN32/64/128, data is clocked on the rising edge of SCK.
When reading data from the AT90CAN32/64/128, data is clocked on the falling edge of SCK.
To program and verify the AT90CAN32/64/128 in the serial programming mode, the following
sequence is recommended (See four byte instruction formats in
MISO (PDO)
MOSI (PDI)
1. If the device is clocked by the internal Oscillator, it is no need to connect a clock source to the
Symbol
SCK
XTAL1 pin.
341.
Pins
PE0
PE1
PB1
ck
ck
PDO
SCK
PDI
< 12 MHz, 3 CPU clock cycles for f
< 12 MHz, 3 CPU clock cycles for f
Table 25-11 on page 341
PE0
PE1
PB1
XTAL1
RESET
GND
(1)
I/O
O
I
I
AVCC
AT90CAN32/64/128
VCC
and the EEPROM parameters in
Table
+2.7 - +5.5V
+2.7 - +5.5V
ck
ck
Serial Data out
Description
Serial Data in
25-15):
Serial Clock
≥ 12 MHz
≥ 12 MHz
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