AT90CAN128-16MJ Atmel, AT90CAN128-16MJ Datasheet - Page 22
![IC MCU AVR FLASH 128K 64-QFN](/photos/12/13/121326/313-64-qfn_sml.jpg)
AT90CAN128-16MJ
Manufacturer Part Number
AT90CAN128-16MJ
Description
IC MCU AVR FLASH 128K 64-QFN
Manufacturer
Atmel
Series
AVR® 90CANr
Specifications of AT90CAN128-16MJ
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
CAN, EBI/EMI, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-VQFN Exposed Pad, 64-HVQFN, 64-SQFN, 64-DHVQFN
For Use With
ATDVK90CAN1 - KIT DEV FOR AT90CAN128 MCU
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
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4.3
4.3.1
4.3.2
22
EEPROM Data Memory
AT90CAN32/64/128
EEPROM Read/Write Access
The EEPROM Address Registers – EEARH and EEARL
The AT90CAN32/64/128 contains EEPROM memory (see “E2 size”). It is organized as a sepa-
rate data space, in which single bytes can be read and written. The EEPROM has an endurance
of at least 100,000 write/erase cycles. The access between the EEPROM and the CPU is
described in the following, specifying the EEPROM Address Registers, the EEPROM Data Reg-
ister, and the EEPROM Control Register.
For a detailed description of SPI, JTAG and Parallel data downloading to the EEPROM, see
“SPI Serial Programming Overview” on page
and
The EEPROM Access Registers are accessible in the I/O space.
The write access time for the EEPROM is given in
lets the user software detect when the next byte can be written. If the user code contains instruc-
tions that write the EEPROM, some precautions must be taken. In heavily filtered power
supplies, V
period of time to run at a voltage lower than specified as minimum for the clock frequency used.
See “Preventing EEPROM Corruption” on page
situations.
In order to prevent unintentional EEPROM writes, a specific write procedure must be followed.
Refer to the description of the EEPROM Control Register for details on this.
When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is
executed. When the EEPROM is written, the CPU is halted for two clock cycles before the next
instruction is executed.
• Bits 15..12 – Reserved Bits
These bits are reserved bits in the AT90CAN32/64/128 and will always read as zero.
• Bits 11..0 – EEAR11..0: EEPROM Address
The EEPROM Address Registers – EEARH and EEARL specify the EEPROM address in the
EEPROM space (see “E2 size”). The EEPROM data bytes are addressed linearly between 0
and “E2 end”. The initial value of EEAR is undefined. A proper value must be written before the
EEPROM may be accessed.
Bit
Read/Write
Initial Value
“Parallel Programming Overview” on page 339
– AT90CAN32: EEAR11 & EEAR10 exist as register bit but they are not used for
– AT90CAN64: EEAR11 exists as register bit but it is not used for addressing.
addressing.
CC
EEAR7
is likely to rise or fall slowly on power-up/down. This causes the device for some
R/W
15
–
7
R
0
X
EEAR6
R/W
14
R
X
–
6
0
EEAR5
R/W
13
R
X
–
5
0
EEAR4
R/W
12
R
X
–
4
0
348,
EEAR11
EEAR3
R/W
R/W
26.for details on how to avoid problems in these
11
X
X
3
“JTAG Programming Overview” on page
respectively.
Table
EEAR10
EEAR2
R/W
R/W
10
2
X
X
4-2. A self-timing function, however,
EEAR9
EEAR1
R/W
R/W
X
X
9
1
EEAR8
EEAR0
R/W
R/W
X
X
8
0
EEARH
EEARL
7679H–CAN–08/08
352,
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