AT89C51SND1C-ROTUL Atmel, AT89C51SND1C-ROTUL Datasheet - Page 100

• Manufacturer Part Number: AT89C51SND1C-ROTUL
• Description: IC 8051 MCU FLASH 64K MP3 80TQFP
• Manufacturer: Atmel
• Series: 89Cr

Specifications of AT89C51SND1C-ROTUL

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, IDE/ATAPI, MMC, SPI, UART/USART, USB
• Peripherals: Audio, I²S, MP3, PCM, POR, WDT
• Number Of I /o: 44
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.3 V
• Data Converters: A/D 2x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP, 80-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

100
AT8xC51SND1C
Reset Value = 0000 0000b
Table 93. USBINT Register
USBINT (S:BDh) – USB Global Interrupt Register
Reset Value = 0000 0000b
Table 94. USBIEN Register
USBIEN (S:BEh) – USB Global Interrupt Enable Register
Number
Number
6 - 0
7 - 6
2 - 1
Bit
Bit
7
7
5
4
3
0
7
-
-
Mnemonic Description
Mnemonic Description
WUPCPU
UADD6:0
EORINT
SOFINT
SPINT
FEN
Bit
Bit
6
6
-
-
-
-
Function Enable Bit
Set to enable the function. The device firmware should set this bit after it has
received a USB reset and participate in the following configuration process with
the default address (FEN is reset to 0).
Cleared by hardware at power-up, should not be cleared by the device firmware
once set.
USB Address Bits
This field contains the default address (0) after power-up or USB bus reset.
It should be written with the value set by a SET_ADDRESS request received by
the device firmware.
Reserved
The value read from these bits is always 0. Do not set these bits.
Wake Up CPU Interrupt Flag
Set by hardware when the USB controller is in SUSPEND state and is re-
activated by a non-idle signal from USB line (not by an upstream resume). This
triggers a USB interrupt when EWUPCPU is set in the USBIEN.
Cleared by software after re-enabling all USB clocks.
End of Reset Interrupt Flag
Set by hardware when a End of Reset has been detected by the USB controller.
This triggers a USB interrupt when EEORINT is set in USBIEN.
Cleared by software.
Start of Frame Interrupt Flag
Set by hardware when an USB Start of Frame packet (SOF) has been properly
received. This triggers a USB interrupt when ESOFINT is set in USBIEN.
Cleared by software.
Reserved
The value read from these bits is always 0. Do not set these bits.
Suspend Interrupt Flag
Set by hardware when a USB Suspend (Idle bus for three frame periods: a J
state for 3 ms) is detected. This triggers a USB interrupt when ESPINT is set in
USBIEN.
Cleared by software.
EWUPCPU
WUPCPU
5
5
EEORINT
EORINT
4
4
ESOFINT
SOFINT
3
3
2
2
-
-
1
1
-
-
4109L–8051–02/08
ESPINT
SPINT
0
0