AT89C51SND1C-ROTUL Atmel, AT89C51SND1C-ROTUL Datasheet - Page 97

• Manufacturer Part Number: AT89C51SND1C-ROTUL
• Description: IC 8051 MCU FLASH 64K MP3 80TQFP
• Manufacturer: Atmel
• Series: 89Cr

Specifications of AT89C51SND1C-ROTUL

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, IDE/ATAPI, MMC, SPI, UART/USART, USB
• Peripherals: Audio, I²S, MP3, PCM, POR, WDT
• Number Of I /o: 44
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.3 V
• Data Converters: A/D 2x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP, 80-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

15.9.2
4109L–8051–02/08
USB Interrupt Control System
Table 1. Priority Levels
As shown in Figure 15-16, many events can produce a USB interrupt:
•
•
•
•
•
•
•
•
TXCMPL: Transmitted In Data
Host accept a In packet.
RXOUTB0: Received Out Data Bank 0
when an Out packet is accepted by the endpoint and stored in bank 0.
RXOUTB1: Received Out Data Bank 1 (only for Ping-pong endpoints)
102). This bit is set by hardware when an Out packet is accepted by the endpoint and stored
in bank 1.
RXSETUP: Received Setup
SETUP packet is accepted by the endpoint.
STLCRC: STALLED (only for Control, Bulk and Interrupt endpoints)
This bit is set by hardware when a STALL handshake has been sent as requested by
STALLRQ, and is reset by hardware when a SETUP packet is received.
SOFINT: Start of Frame Interrupt
USB start of frame packet has been received.
WUPCPU: Wake-Up CPU Interrupt
when a USB resume is detected on the USB bus, after a SUSPEND state.
SPINT: Suspend Interrupt
suspend is detected on the USB bus.
IPHUSB
0
0
1
1
(Table 93 on page
(Table 97 on page
(Table 97 on page
(Table 93 on page
IPLUSB
(Table 93 on page
0
1
0
1
(Table 97 on page
100). This bit is set by hardware when a USB
102). This bit is set by hardware when an
102). This bit is set by hardware when the
100). This bit is set by hardware when a
100). This bit is set by hardware
102). This bit is set by hardware
AT8xC51SND1C
3..................Highest
USB Priority Level
0..................Lowest
(Table 97 on page
(Table 97 on page
1
2
102).
97