AT89C51SND1C-ROTUL Atmel, AT89C51SND1C-ROTUL Datasheet - Page 57

• Manufacturer Part Number: AT89C51SND1C-ROTUL
• Description: IC 8051 MCU FLASH 64K MP3 80TQFP
• Manufacturer: Atmel
• Series: 89Cr

Specifications of AT89C51SND1C-ROTUL

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, IDE/ATAPI, MMC, SPI, UART/USART, USB
• Peripherals: Audio, I²S, MP3, PCM, POR, WDT
• Number Of I /o: 44
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.3 V
• Data Converters: A/D 2x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP, 80-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

11.4.1
11.4.2
11.4.3
11.4.4
11.5
Figure 11-10. Timer Interrupt System
11.6
4109L–8051–02/08
Interrupt
Registers
Mode 0 (13-bit Timer)
Mode 1 (16-bit Timer)
Mode 2 (8-bit Timer with Auto-Reload)
Mode 3 (Halt)
•
•
Mode 0 configures Timer 1 as a 13-bit Timer, which is set up as an 8-bit Timer (TH1 register)
with a modulo-32 prescaler implemented with the lower 5 bits of the TL1 register (see Figure 11-
2). The upper 3 bits of TL1 register are ignored. Prescaler overflow increments TH1 register.
Mode 1 configures Timer 1 as a 16-bit Timer with TH1 and TL1 registers connected in cascade
(see Figure 11-4). The selected input increments TL1 register.
Mode 2 configures Timer 1 as an 8-bit Timer (TL1 register) with automatic reload from TH1 reg-
ister on overflow (see Figure 11-6). TL1 overflow sets TF1 flag in TCON register and reloads
TL1 with the contents of TH1, which is preset by software. The reload leaves TH1 unchanged.
Placing Timer 1 in mode 3 causes it to halt and hold its count. This can be used to halt Timer 1
when TR1 run control bit is not available i.e. when Timer 0 is in mode 3.
Each Timer handles one interrupt source that is the timer overflow flag TF0 or TF1. This flag is
set every time an overflow occurs. Flags are cleared when vectoring to the Timer interrupt rou-
tine. Interrupts are enabled by setting ETx bit in IEN0 register. This assumes interrupts are
globally enabled by setting EA bit in IEN0 register.
Table 61. TCON Register
TCON (S:88h) – Timer/Counter Control Register
When Timer 0 is in mode 3, it uses Timer 1’s overflow flag (TF1) and run control bit (TR1).
For this situation, use Timer 1 only for applications that do not require an interrupt (such as a
Baud Rate Generator for the Serial Port) and switch Timer 1 in and out of mode 3 to turn it
off and on.
It is important to stop the Timer/Counter before changing modes.
TCON.5
TCON.7
TF0
TF1
TF1
7
TR1
6
IEN0.1
IEN0.3
ET0
ET1
TF0
5
Timer 0
Interrupt Request
Timer 1
Interrupt Request
TR0
4
IE1
3
AT8xC51SND1C
IT1
2
IE0
1
IT0
0
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