AT89C51SND1C-ROTUL Atmel, AT89C51SND1C-ROTUL Datasheet - Page 149

• Manufacturer Part Number: AT89C51SND1C-ROTUL
• Description: IC 8051 MCU FLASH 64K MP3 80TQFP
• Manufacturer: Atmel
• Series: 89Cr

Specifications of AT89C51SND1C-ROTUL

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, IDE/ATAPI, MMC, SPI, UART/USART, USB
• Peripherals: Audio, I²S, MP3, PCM, POR, WDT
• Number Of I /o: 44
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.3 V
• Data Converters: A/D 2x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP, 80-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Figure 19-4. SPI Slave Mode Block Diagram
Note:
19.1.3
19.1.4
4109L–8051–02/08
1. MSTR bit in SPCON is cleared to select slave mode.
Bit Rate
Data Transfer
MISO/P4.2
MOSI/P4.1
SCK/P4.2
SS/P4.3
When the AT8xC51SND1C is the only slave on the bus, it can be useful not to use SS pin and
get it back to I/O functionality. This is achieved by setting SSDIS bit in SPCON. This bit has no
effect when CPHA is cleared (see Section "SS Management", page 150).
The bit rate can be selected from seven predefined bit rates using the SPR2, SPR1 and SPR0
control bits in SPCON according to Table 132. These bit rates are derived from the peripheral
clock (F
Table 132. Serial Bit Rates
Notes:
The Clock Polarity bit (CPOL in SPCON) defines the default SCK line level in idle state
the Clock Phase bit (CPHA in SPCON) defines the edges on which the input data are sampled
and the edges on which the output data are shifted (see Figure 19-5 and Figure 19-6). The SI
signal is output from the selected slave and the SO signal is the output from the master. The
AT8xC51SND1C captures data from the SI line while the selected slave captures data from the
SO line.
PER
1. These frequencies are achieved in X1 mode, F
2. These frequencies are achieved in X2 mode, F
SPR2
0
0
0
0
1
1
1
1
) issued from the Clock Controller block as detailed in Section "Oscillator", page 13.
SPCON.5
SSDIS
SPR1
0
0
1
1
0
0
1
1
Control and Clock Logic
SPR0
0
1
0
1
0
1
0
1
SPCON.2
CPHA
6 MHz
46.875
187.5
93.75
3000
1500
6000
750
375
(1)
SPCON.3
CPOL
8 MHz
4000
2000
1000
8000
62.5
500
250
125
(1)
10 MHz
Bit Rate (kHz) Vs F
156.25
78.125
10000
312.5
5000
2500
1250
625
I
SPSTA.7
SPIF
(1)
8-bit Shift Register
PER
PER
12 MHz
SPDAT RD
12000
SPDAT WR
= F
= F
187.5
93.75
6000
3000
1500
750
375
OSC
OSC
(2)
PER
.
÷ 2.
AT8xC51SND1C
16 MHz
16000
8000
4000
2000
1000
500
250
125
(2)
Q
20 MHz
156.25
10000
20000
312.5
5000
2500
1250
625
(2)
F
PER
128
(1)
16
32
64
Divider
2
4
8
1
while
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