ATMEGA8HVD-4MX Atmel, ATMEGA8HVD-4MX Datasheet
ATMEGA8HVD-4MX
Specifications of ATMEGA8HVD-4MX
Related parts for ATMEGA8HVD-4MX
ATMEGA8HVD-4MX Summary of contents
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... CC • Maximum Withstand Voltage (VFET): 12V • Maximum Withstand Voltage (High-voltage pins): 5V • Temperature Range: -20°C to 85°C • Speed Grade MHz ® 8-bit Microcontroller (1) 8-bit Microcontroller with 4K/8K Bytes In-System Programmable Flash ATmega4HVD ATmega8HVD Preliminary 8052B–AVR–09/08 ...
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Pin Configurations Figure 1-1. Dual Row DFN/ MLF-pinout ATmega4HVD/8HVD Table 1-1. Dual Row DFN/ MLF-pinout ATmega4HVD/8HVD DNC BATT GND PV1 VFET VREG B ATmega4HVD/8HVD 2 Top view Bottom ...
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Pin Descriptions 1.1.1 VFET Input to the internal voltage regulator. 1.1.2 VCC Pin for connection of external decoupling capacitor. VCC is internally connected to the voltage regulator output VREG. 1.1.3 VREG Output from the internal voltage regulator. Internally connected ...
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... The chip utilizes Atmel's Deep Under-voltage Recovery (DUVR) mode that supports pre- charging of deeply discharged battery cells without using a separate Pre-charge FET. An enhanced start-up scheme allows the chip to operate correctly even with only Discharge FET connected ...
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... CISC microcontrollers. The device is manufactured using Atmel’s high voltage high density non-volatile memory tech- nology. The On-chip ISP Flash allows the program memory to be reprogrammed In-System conventional non-volatile memory programmer On-chip Boot program running on the AVR core ...
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AVR CPU Core 6.1 Overview This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control ...
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Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space addressing – enabling efficient address calculations. One of the these address pointers can also be used as an address pointer for look ...
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SREG – AVR Status Register Bit Read/Write Initial Value • Bit 7 – I: Global Interrupt Enable The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual interrupt enable control is then performed ...
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General Purpose Register File The Register File is optimized for the AVR Enhanced RISC instruction set. In order to achieve the required performance and flexibility, the following input/output schemes are supported by the Register File: • One 8-bit output ...
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Figure 6-3. X-register Y-register Z-register In the different addressing modes these address registers have functions as fixed displace- ment, automatic increment, and automatic decrement (see the instruction set reference for details). 6.5 Stack Pointer The Stack is mainly used for ...
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Instruction Execution Timing This section describes the general access timing concepts for instruction execution. The AVR CPU is driven by the CPU clock clk the chip. No internal clock division is used. Figure 6-4 Harvard architecture and the fast-access ...
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When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are dis- abled. The user software can write logic one to the I-bit to enable nested interrupts. All enabled interrupts can then interrupt the current interrupt ...
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When using the SEI instruction to enable interrupts, the instruction following SEI will be exe- cuted before any pending interrupts, as shown in this example. Assembly Code Example C Code Example 6.7.1 Interrupt Response Time The interrupt execution response for ...
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AVR Memories 7.1 Overview This section describes the different memories in the ATmega4HVD/8HVD. The AVR architec- ture has two main memory spaces, the Data Memory and the Program Memory space. In addition, the ATmega4HVD/8HVD features an EEPROM Memory for ...
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SRAM Data Memory Figure 7-2 The ATmega4HVD/8HVD is a complex microcontroller with more peripheral units than can be supported within the 64 locations reserved in the Opcode for the IN and OUT instructions. For the Extended I/O space from ...
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Figure 1. On-chip Data SRAM Access Cycles 7.4 EEPROM Data Memory The ATmega4HVD/8HVD contains 256 bytes of data EEPROM memory organized as a separate data space, in which single bytes can be read and written. The EEPROM has ...
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Refer to the instruction set section for more details. When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, ...
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EECR – The EEPROM Control Register Bit Read/Write Initial Value • Bits 7:6 – Res: Reserved Bits These bits are reserved bits in the ATmega4HVD/8HVD and will always read as zero. • Bits 5, 4 – EEPM1 and EEPM0: ...
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Write a logical one to the EEMPE bit while writing a zero to EEPE in EECR. 5. Within four clock cycles after setting EEMPE, write a logical one to EEPE. Caution: An interrupt between step 4 and step 5 ...
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Assembly Code Example EEPROM_write: C Code Example void EEPROM_write(unsigned int uiAddress, unsigned char ucData ATmega4HVD/8HVD 20 ; Wait for completion of previous write sbic EECR,EEWE rjmp EEPROM_write ; Set up address (r17) in address register out EEARL, r17 ...
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The next code examples show assembly and C functions for reading the EEPROM. The examples assume that interrupts are controlled so that no interrupts will occur during execu- tion of these functions. Assembly Code Example C Code Example 7.6.4 GPIOR2 ...
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System Clock and Clock Options 8.1 Clock Systems and their Distribution Figure 8-1 clocks need not be active at a given time. In order to reduce power consumption, the clocks to modules not being used can be halted by ...
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ADC. The dedicated ADC clock allows halting the CPU and I/O clocks in order to reduce noise generated by digital circuitry. This gives more accurate ADC conversion results. 8.1.5 Watchdog Timer and Battery Protection Clock The Watchdog Timer and Current ...
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Slow RC Oscillator The Slow RC Oscillator provides a 131 kHz clock (typical value, refer to section "Electrical Characteristics" on page 164 for details). This clock can be used as a timing reference for run- time calibration of the ...
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Table 8-2. Note: 8.9 Clock Output The CPU clock divided by 2 can be output to the PB2 pin. The CPU can enable the clock out- put function by setting the CKOE bit in the ...
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Interrupts must be disabled when changing prescaler setting to make sure the write procedure is not interrupted. 8.11 ADC Clock Prescaler The ADC clock will be automatically prescaled relative to the System Clock Prescaler settings, see ”System Clock Prescaler” on ...
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OSI – Oscillator Sampling Interface 8.12.1 Features • Runtime selectable oscillator input (Slow RC or ULP RC Oscillator) • 7 bit prescaling of the selected oscillator • Software read access to the phase of the prescaled clock • Input ...
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Usage The Slow RC oscillator represents a highly predictable and accurate clock source over the entire temperature range and provides an excellent reference for calibrating the Fast RC oscil- lator runtime. Typically, runtime calibration is needed to provide an ...
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Register Description 8.13.1 FOSCCAL – Fast RC Oscillator Calibration Register Bit Read/Write Initial Value • Bits 7:0 – FCAL7:0: Fast RC Oscillator Calibration Value The Fast RC Oscillator Calibration Register is used to trim the Fast RC Oscillator to ...
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Bit 7 – CLKPCE: Clock Prescaler Change Enable The CLKPCE bit must be written to logic one to enable change of the CLKPS bits. The CLK- PCE bit is only updated when the other bits in CLKPR are simultaneously ...
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Bit 0 – OSIEN: Oscillator Sampling Interface Enable Setting this bit enables the Oscillator Sampling Interface. When this bit is cleared, the Oscilla- tor Sampling Interface is disabled. Notes: 8052B–AVR–09/08 1. The prescaler is reset each time the OSICSR ...
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Power Management and Sleep Modes Sleep modes enable the application to shut down unused modules in the MCU, thereby saving power. The AVR provides various sleep modes allowing the user to tailor the power consump- tion to the application’s ...
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Figure 9-1. Charger Detected/ Power-on Reset Note: Table 9-2. Module RCOSC_FAST RCOSC_ULP RCOSC_SLOW CPU Flash Timer/ Counter n ADC External Interrupts CBP WDT 8052B–AVR–09/08 Sleep Mode State Diagram RESET from all States RESET Active Sleep Interrupt Idle BLOD_PWROFF Power-off 1. ...
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Table 9-2. Module VREG CHARGER_DETECT VREGMON OSI Notes: 9.2 Idle Mode When the SM2:0 bits are written to 000, the SLEEP instruction makes the MCU enter Idle mode, stopping the CPU but allowing all peripheral functions to continue operating. This ...
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Power-off Mode When the SM2:0 bits are written to 100 and the SE bit is set, the SLEEP instruction makes the CPU shut down the Voltage Regulator, leaving only the Charger Detect Circuitry operational. To ensure that the MCU ...
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On-chip Debug System A programmed DWEN Fuse enables some parts of the clock system to be running in all sleep modes. This will increase the power consumption while in sleep. Thus, the DWEN Fuse should be disabled when debugWire ...
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Table 9-3. • Bit 0 – SE: Sleep Enable The SE bit must be written to logic one to make the MCU enter the sleep mode when the SLEEP instruction is executed. To avoid the MCU entering the sleep mode ...
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System Control and Reset 10.1 Resetting the AVR During reset, all I/O Registers are set to their initial values, and the program starts execution from the Reset Vector. The instruction placed at the Reset Vector must be a JMP ...
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Figure 10-1. Reset Logic 8052B–AVR–09/ Black-out Detection/ V FET Power-on Reset Circuit/ BATT Charger Detect V CC Pull-up Resistor SPIKE RESET Reset Circuit FILTER dW debugWIRE Watchdog Timer SlowRC Oscillator Clock Generator SUT[2:0] ATmega4HVD/8HVD DATA BUS MCU Status ...
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External Reset An External Reset is generated by a low level on the RESET pin. Reset pulses longer than the minimum pulse width (see reset, even if the clock is not running. Shorter pulses are not guaranteed to generate ...
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Power-off mode. The algorithm used for switch- ing between the two V the V Figure 10-4. BLOD levels switching Notice that during the Power-On Reset start-up sequence, a Black-out detection will only ...
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Figure 10-7. Black-out Reset with high current consumption at V Internal Reset 10.6 ATmega4HVD/8HVD Start-up Sequence The Voltage Regulator will not start until it is enabled by the Charger Detect module. Before this happens the chip will be in Power-off ...
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Power-on Reset (POR) is generated. During the initial start-up when a valid reference for the voltage regulator is missing, VCC is driven as close as possible to VFET. Voltage regulation will only start when ...
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Figure 10-9. Powering up ATmega4HVD/8HVD (2-FET example) During the initial start-up when a valid reference for the voltage regulator is missing, VCC is driven as close as possible to VFET. Voltage regulation will only start when VCC has reached VBLOT, ...
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Watchdog Timer 10.7.1 Features • Clocked from Slow RC Oscillator • 3 Operating modes – Interrupt – System Reset – Interrupt and System Reset • Selectable Timeout period from • Possible Hardware fuse Watchdog always ...
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In the same operation, write a logic one to the Watchdog change enable bit (WDCE) and WDE. A logic one must be written to WDE regardless of the previous value of the WDE bit. 2. Within the next four ...
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Note: If the Watchdog is accidentally enabled, for example by a runaway pointer or Black-out condition, the device will be reset and the Watchdog Timer will stay enabled. If the code is not set up to handle the Watchdog, this ...
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Register Description 10.8.1 MCUSR – MCU Status Register The MCU Status Register provides information on which reset source caused an MCU reset. Bit Read/Write Initial Value • Bits 7:4, 2 – Res: Reserved Bits These bits are reserved, and ...
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If WDE is set, the Watchdog Timer is in Interrupt and System Reset Mode. The first timeout in the Watchdog Timer will set WDIF. Executing the corresponding interrupt vector will clear WDIE and WDIF automatically by hardware (the Watchdog goes ...
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Table 10-2. Watchdog Timer Prescale Select (Typical Timeout at V WDP3 WDP2 WDP1 WDP0 ...
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Interrupts This section describes the specifics ATmega4HVD/8HVD. For a general explanation of ...
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Address Labels Code 0x0000 rjmp 0x0001 rjmp 0x0002 rjmp 0x0003 rjmp 0x0004 rjmp 0x0005 rjmp 0x0006 rjmp 0x0007 rjmp 0x0008 rjmp 0x0009 rjmp 0x000A rjmp 0x000B rjmp 0x000C rjmp 0x000D rjmp 0x000E rjmp 0x000F rjmp ; 0x000F RESET: ldi 0x0010 ...
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External Interrupt The External Interrupts are triggered by the INT1:0 pins. Observe that, if enabled, the interrupt will trigger even if the INT1:0 pins are configured as outputs. This feature provides a way of generating a software interrupt. The ...
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Finally, the INTn interrupt flags should be cleared by writing a logical one to its Interrupt Flag bit (INTFn) in the EIFR Register before the interrupt is re-enabled. Table 12-1. ISCn1 Note: 12.1.2 EIMSK ...
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Alternatively, the flag can be cleared by writing a logical one to it. This flag is always cleared when INT1:0 are configured as level interrupt. Note that when entering sleep mode with the INT1:0 interrupt disabled, ...
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High Voltage I/O Ports All high voltage AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the state of one port pin can be changed without unintention- ally changing the state of ...
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High Voltage Ports as General Digital Outputs The high voltage ports are high voltage tolerant open collector output ports. a functional description of one output port pin, here generically called Pxn. Figure 13-2. General High Voltage Digital I/O Note: ...
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Figure 13-3. High Voltage Digital I/O Note: Table 13-1 Figure 13-3 internally in the modules having the alternate function. Table 13-1. Signal Name PVOE PVOV DIEOE DIEOV DI ATmega4HVD/8HVD 58 (1) Pxn DIEOExn DIEOVxn 1 0 PVOExn: Pxn PORT VALUE ...
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Alternate Functions of Port C The Port C pins with alternate functions are shown in Table 13-2. The alternate pin configuration is as follows: • INT0/ICP0/XTAL - Port C, Bit 0 INT0, External Interrupt 0: When INT0 is written ...
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Register Description 13.3.1 PORTC – Port C Data Register Bit Read/Write Initial Value 13.3.2 PINC – Port C Input Pins Address Bit Read/Write Initial Value ATmega4HVD/8HVD – – – – ...
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Low Voltage I/O-Ports 14.1 Overview All low voltage AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without uninten- tionally changing the direction ...
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Note that enabling the alternate function of some of the port pins does not affect the use of the other pins in the port as general digital I/O. 14.2 Low Voltage Ports as General Digital I/O The low voltage ports ...
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If PORTxn is written logic one when the pin is configured as an output pin, the port pin is driven high (one). If PORTxn is written logic zero when the pin is configured as an output pin, the port pin ...
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Figure 14-3. Synchronization when Reading an Externally Applied Pin value Consider the clock period starting shortly after the first falling edge of the system clock. The latch is closed when the clock is low, and goes transparent when the clock ...
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Assembly Code Example C Code Example Note: 14.2.5 Digital Input Enable and Sleep Modes As shown in input of the schmitt-trigger. The signal denoted SLEEP in the figure, is set by the MCU Sleep Controller in Power-save mode to avoid ...
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Unconnected Pins If some pins are unused recommended to ensure that these pins have a defined level. Even though most of the digital inputs are disabled in the deep sleep modes as described above, floating inputs should ...
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Figure 14-5. Alternate Port Functions Note: Table 14-2 on page 68 indexes from generated internally in the modules having the alternate function. 8052B–AVR–09/08 (1) PUOExn PUOVxn 1 0 DDOExn DDOVxn 1 0 PVOExn PVOVxn 1 Pxn 0 DIEOExn DIEOVxn 1 ...
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Table 14-2. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO The following subsections shortly describe the alternate functions for each port, and relate the overriding signals to the alternate function. Refer to the alternate function ...
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Alternate Functions of Port B The Port B pins with alternate functions are shown in Table 14-3. The alternate pin configuration is as follows: • MISO/CKOUT/T1 - Port B, Bit 2 MISO : Slave Data Output pin for SPI ...
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Register Description 14.4.1 MCUCR – MCU Control Register Bit Read/Write Initial Value • Bit 4 – PUD: Pull-up Disable When this bit is written to one, the pull-ups in the I/O ports are disabled even if the DDxn and ...
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Timer/Counter0 and Timer/Counter1 Prescalers 15.1 Overview Timer/Counter1 and Timer/Counter0 share the same prescaler module, but the Timer/Coun- ters can have different prescaler settings. The description below applies to both Timer/Counter1 and Timer/Counter0. 15.2 Internal Clock Source The Timer/Counter can ...
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External Clock Source An external clock source applied to the Tn pin can be used as Timer/Counter clock (clk Tn pin is sampled once every system clock cycle by the pin synchronization logic. The syn- chronized (sampled) signal is ...
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Table 15-1. CSn2 external pin modes are used for the Timer/Counter n, transitions on the Tn pin will clock the counter even if the pin is configured as an output. This ...
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Timer/Counter(T/C0,T/C1) 16.1 Features • Clear Timer on Compare Match (Auto Reload) • Input Capture unit • Four Independent Interrupt Sources (TOVn, OCFnA, OCFnB, ICFn) • 8-bit Mode with Two Independent Output Compare Units • 16-bit Mode with One Independent ...
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Registers The Timer/Counter Low Byte Register (TCNTnL) and Output Compare Registers (OCRnA and OCRnB) are 8-bit registers. Interrupt request (abbreviated to Int.Req. in 74) signals are all visible in the Timer Interrupt Flag Register (TIFR). All interrupts are individu- ...
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Figure 16-2. Counter Unit Block Diagram Signal description (internal signals): The counter is incremented at each timer clock (clk restarts from BOTTOM. The counting sequence is determined by the setting of the WGMn0 bits located in the Timer/Counter Control Register ...
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Normal 8-bit Mode In the normal mode, the counter (TCNTnL) is incrementing until it overruns when it passes its maximum 8-bit value (MAX = 0xFF) and then restarts from the bottom (0x00), see on page 76 as the TCNTnL ...
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Normal mode, a new counter value can be written any- time. The Output Compare Unit can be used to generate interrupts at some given time. 16.5.4 Clear Timer on Compare Match (CTC) ...
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Figure 16-4. Input Capture Unit Block Diagram The Output Compare Register OCRnA is a dual-purpose register that is also used as an 8-bit Input Capture Register ICRn. In 16-bit Input Capture mode the Output Compare Register OCRnB serves as the ...
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Noise Canceler The noise canceler improves noise immunity by using a simple digital filtering scheme. The noise canceler input is monitored over four samples, and all four must be equal for changing the output that in turn is used ...
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OCFnA as there is only one Output Compare Unit. If the corresponding interrupt is enabled, the Output Compare Flag generates an Output Compare interrupt. The Output Compare Flag is automatically cleared when the interrupt is executed. Alternatively, the flag can ...
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Figure 16-7. Timer/Counter Timing Diagram, with Prescaler (f clk clk (clk TCNTn TOVn Figure 16-8 on page 82 Figure 16-8. Timer/Counter Timing Diagram, Setting of OCFnx, with Prescaler (f (clk TCNTn OCRnx OCFnx Figure 16-9 on page 82 Figure 16-9. ...
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There is one exception in the temporary register usage. In the Output Compare mode the 16- bit Output Compare Register OCRnA/B is read without the temporary register, because the Output Compare Register contains a fixed value that is only changed ...
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The following code examples show how atomic read of the TCNTn register contents. Reading any of the OCRn register can be done by using the same principle. Assembly Code Example TIMn_ReadTCNTn: C Code Example unsigned int TIMn_ReadTCNTn( ...
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The following code examples show how atomic write of the TCNTnH/L register con- tents. Writing any of the OCRnA/B registers can be done by using the same principle. Note: The assembly code example requires that the r17:r16 ...
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Register Description 16.10.1 TCCRnA – Timer/Counter n Control Register A Bit Read/Write Initial Value • Bit 7– TCWn: Timer/Counter Width When this bit is written to one 16-bit mode is selected. The Timer/Counter width is set to 16- bits ...
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TCNTnL – Timer/Counter n Register Low Byte Bit Read/Write Initial Value The Timer/Counter Register TCNTnL gives direct access, both for read and write operations, to the Timer/Counter unit 8-bit counter. Writing to the TCNTnL Register blocks (disables) the Compare ...
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In 16-bit mode the OCRnB register contains the high byte of the 16-bit Output Compare Reg- ister. To ensure that both the high and the low bytes are written simultaneously when the CPU writes to these registers, the access is ...
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Bit 2 – OCFnB: Output Compare Flag n B The OCFnB bit is set when a Compare Match occurs between the Timer/Counter and the data in OCRnB – Output Compare Register n B. OCFnB is cleared by hardware when ...
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ADC - Analog-to-Digital Converter 17.1 Features • 10-bit Resolution • 78 µs Conversion Time @ clk • kSPS at Maximum Resolution • External Input Channel with Input Voltage Range • External Input Channel ...
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Operation The ADC converts an analog input voltage to a 10-bit digital value through successive approx- imation. For the PV1 pin the minimum value represents GND and the maximum value represents 5 times the internal 1.1V reference voltage. For ...
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Figure 17-2. ADC Timing Diagram, First Conversion (Single Conversion Mode) Cycle Number ADC Clock ADEN ADSC ADIF ADCH ADCL Figure 17-3. ADC Timing Diagram, Single Conversion Cycle Number ADC Clock ADSC ADIF ADCH ADCL Table 17-1. Condition First conversion Normal ...
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CPU before the ADC conversion is complete, that inter- rupt will be executed, and an ADC Conversion Complete interrupt request will be generated when the ADC conversion completes. The CPU will remain in active mode ...
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ADC Accuracy Definitions An n-bit single-ended ADC converts a voltage linearly between GND and V (LSBs). The lowest code is read as 0, and the highest code is read as 2 Several parameters describe the deviation from the ideal ...
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Figure 17-7. Integral Non-linearity (INL) • Differential Non-linearity (DNL): The maximum deviation of the actual code width (the interval between two adjacent transitions) from the ideal code width (1 LSB). Ideal value: 0 LSB. Figure 17-8. Differential Non-linearity (DNL) • ...
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ADC Conversion Result After the conversion is complete (ADIF is high), the conversion result can be found in the ADC Result Registers (ADCL, ADCH). For single ended conversion, the result is where V ground, and 0x3FF represents 5 times ...
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Register Description 17.8.1 ADCSRA – ADC Control and Status Register A Bit Read/Write Initial Value • Bit 7 – ADEN: ADC Enable Writing this bit to one enables the ADC. By writing it to zero, the ADC is turned ...
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Table 17-3. 17.8.2 ADCL and ADCH – The ADC Data Register Bit Read/Write Initial Value When an ADC conversion is complete, the result is found in these two registers.When ADCL is read, the ADC Data Register is not updated until ...
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Voltage Reference ATmega4HVD/8HVD features an internal bandgap reference. This reference is an input refer- ence to the ADC, the Battery Protection module, the Voltage Regulator, and the Black-out Detection. The bandgap reference voltage cannot be observed directly at any ...
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Voltage Regulator 19.1 Features • Linear regulation giving a fixed output voltage (VREG) of 2.2V for VFET > V Output voltage forced as close as possible to VFET for VFET ≤ V • operation. • Regulator Short-circuit Detection (RSCD), ...
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Battery Pack Short mode The Voltage Regulator has a separate Short-Circuit Detection mode (RSCD) that can be enabled or disabled by SW. This mode should always be enabled except when operating at VFET voltages below V operation during short ...
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V DROP Figure 19-2. Regulator Short-circuit Detection Example V FORCE+ V FORCE- V BLOT, normal 19.5 Register Description 19.5.1 ROCR – Regulator Operating Condition Register Bit Read/Write Initial Value • Bit 7 – ROCS: ROC Status When the VFET voltage ...
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This bit enables the interrupt caused by the ROCWIF Flag. 8052B–AVR–09/08 ATmega4HVD/8HVD 103 ...
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Battery Protection 20.1 Features • Short-circuit Protection • Discharge Over-current Protection • Charge Over-current Protection • External Protection Input • Programmable and Lockable Detection Levels and Reaction Times • Autonomous Operation Independent of CPU 20.2 Overview The Current Battery ...
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The Current Battery Protection (CBP) monitors the cell current by sampling the shunt resistor voltage (R amplifies the voltage with a suitable gain. The output from the operational amplifier is com- pared to an accurate, programmable On-chip voltage reference by ...
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External Protection Input The External Protection Input disables both FETs (Charge FET and Discharge FET) immedi- ately (asynchronously) when the voltage on PC1 is pulled high (logic ‘1’) by the External Protection circuitry also used to disable ...
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Figure 20-1. Example in External protection Input Chip operating mode < Active > < Note: 8052B–AVR–09/08 FCSR [CFE] FCSR [DFE] PC1 INT1 P-save ensure that the FET switch ON time is as expected, the chip should ...
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Battery Protection CPU Interface The Battery Protection CPU Interface is illustrated in Figure 20-2. Battery Protection CPU Interface Each protection originating from the Current Battery Protection module has an Interrupt Flag. All enabled flags are combined into a single ...
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Bit 1 – BPPLE: Battery Protection Parameter Lock Enable • Bit 0 – BPPL: Battery Protection Parameter Lock The BPCR, BPOCTR, BPSCTR, BPDOCD, BPCOCD and BPSCD Battery Protection regis- ters can be locked from any further software updates. Once ...
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BPSCTR – Battery Protection Short-current Timing Register Bit Read/Write Initial Value • Bit 7 – Res: Reserved Bits This bit is reserved and will always read as zero. • Bit 6:0 – SCPT6:0: Short-current Protection Timing These bits control ...
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Table 20-3. Notes: Note: 20.8.5 BPSCD – Battery Protection Short-circuit Detection Level Register Bit Read/Write Initial Value • Bits 7:0 – SCDL7:0: Short-circuit Detection Level These bits sets the R as defined in Note: 8052B–AVR–09/08 Over-current Protection Reaction Time. OCPT[5:0] ...
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BPDOCD – Battery Protection Discharge-Over-current Detection Level Register Bit Read/Write Initial Value • Bits 7:0 – DOCDL7:0: Discharge Over-current Detection Level These bits sets the R Table 20-4 on page Note: 20.8.7 BPCOCD – Battery Protection Charge-Over-current Detection Level ...
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BPIMSK – Battery Protection Interrupt Mask Register Bit Read/Write Initial Value • Bit 7:5 – Res: Reserved Bits These bits are reserved and will always read as zero. • Bit 4 – SCIE: Short-circuit Protection Activated Interrupt The SCIE ...
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FET Control 21.1 Overview The FET control is used to enable and disable the Charge FET and Discharge FET. Normally, the FETs are enabled and disabled by SW writing to the FET Control and Status Register (FCSR). However, the ...
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FET Driver 21.2.1 Features • Charge-pump for generating suitable gate drive for N-Channel FET switch on high side • Deep Under-voltage Recovery mode that allows normal operation while charging a Deeply Over-discharged battery from 0-volt 21.2.2 Overview The ATmega4HVD/8HVD ...
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Figure 21-3. Switching NFET on and off during NORMAL operation ATmega4HVD/8HVD 116 12.0 11.0 10.0 9.0 8.0 7.0 6.0 5.0 4.0 3.0 2.0 1.0 0.0 -1.0 100 200 Time (ms) 8052B–AVR–09/08 300 ...
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DUVR – Deep Under-Voltage Recovery Mode operation The purpose of DUVR mode is to control the Charge FET so that the VFET voltage is above the minimum operating voltage while charging cells below minimum operating voltage. This is useful ...
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Bit 1 – DFE: Discharge FET Enable When the DFE bit is cleared (zero), the Discharge FET will be disabled regardless of the state of the Battery Protection circuitry. When this bit is set (one), the Discharge FET is ...
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On-chip Debug System 22.1 Features • Complete Program Flow Control • Emulates All On-chip Functions, both Digital and Analog, except RESET Pin • Real-time Operation • Symbolic Debugging Support (Both at C and Assembler Source Level, or for ...
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Capacitors connected to the RESET pin must be disconnected when using debugWire. • All external reset sources must be disconnected. 22.4 Software Break Points debugWIRE supports Program memory Break Points by the AVR Break instruction. Setting a Break Point ...
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Self-Programming the Flash 23.1 Overview In ATmega4HVD/8HVD, there is no Read-While-Write support, and no separate Boot Loader Section. The SPM instruction can be executed from the entire Flash. The device provides a Self-Programming mechanism for downloading and uploading program ...
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Performing a Page Write To execute Page Write, set up the address in the Z-pointer, write “00000101” to SPMCSR and execute SPM within four clock cycles after writing SPMCSR. The data in R1 and R0 is ignored. The page ...
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EEPROM Write Prevents Writing to SPMCSR Note that an EEPROM write operation will block all software programming to Flash. Reading the Fuses and Lock bits from software will also be prevented during the EEPROM write opera- tion ...
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CPU itself can execute instructions incorrectly, if the supply voltage for executing instructions is too low. Flash corruption can easily be avoided by following these design recommendations (one is sufficient): 1. Keep the AVR RESET active (low) during ...
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Table 23-1. Signature Byte Description ADC Cell Gain Calibration Word L ADC Cell Gain Calibration Word H ADC Cell Offset Reserved ADC ADC0 Gain Calibration Word L ADC ADC0 Gain Calibration Word H ADC ADC0 Offset Reserved HOT TEMP Reserved ...
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... Program Counter word address: Word select, for PC[4:0] Z5:Z1 filling temporary buffer (must be zero during Page Write operation) Explanation of different variables used in pointer for ATmega8HVD Corresponding Z-value Most significant bit in the Program Counter. (The 11 Program Counter is 12 bits PC[11:0]) Most significant bit which is used to address the ...
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Register Description 23.6.1 SPMCSR – Store Program Memory Control and Status Register The Store Program Memory Control and Status Register contains the control bits needed to control the Program memory operations. Bit Read/Write Initial Value • Bits 7:6 – ...
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This bit enables the SPM instruction for the next four clock cycles. If written to one together with either CTPB, RFLB, PGWRT, or PGERS, the following SPM instruction will have a spe- cial meaning, see description above. If only SPMEN ...
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Memory Programming 24.1 Program And Data Memory Lock Bits The ATmega4HVD/8HVD provides two Lock bits which can be left unprogrammed (“1”) or can be programmed (“0”) to obtain the additional features listed in only be erased to “1” with ...
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... The signature bytes of ATmega4HVD/8HVD is given in Table Table 24-5. Part ATmega4HVD ATmega8HVD ATmega4HVD/8HVD 130 1. The default OSCSEL1:0 setting should not be changed. OSCSEL1:0 = ‘00’ is reserved for test purposes. Other values are reserved for future use. Fuse Low Byte ...
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... No. of Words in a Page and No. of Pages in the EEPROM Device EEPROM Size ATmega4HVD 256 bytes ATmega8HVD 256 bytes 24.6 Serial Downloading Both the Flash and EEPROM memory arrays can be programmed using the serial SPI bus while RESET is pulled to GND. The serial interface consists of pins SCK, MOSI (input) and MISO (output) ...
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Table 24-8. The minimum low and high periods for the serial clock (SCK) input are defined as follows: Low: > 2.2 CPU clock cycles for f High: > 2.2 CPU clock cycles for f 24.6.1 Serial Programming Algorithm When writing ...
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When using EEPROM page access only byte locations loaded with the Load EEPROM Memory Page instruction is altered. The remaining locations remain unchanged. If polling (RDY/BSY) is not used, the used must wait at least t before issuing the ...
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... Refer to the correspondig section for Fuse and Lock bits, Calibration and Signature bytes and Page size. 6. Instructions accessing program memory use word address. This address may be random within the page range. 7. See htt://www.atmel.com/avr for Application Notes regarding programming and programmers. If the LSB in RDY/BSY data byte out is ‘1’, a programming operation is still pending. Wait until this bit returns ‘ ...
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Figure 24-2. Serial Programming Instruction example Load Program Memory Page (High/Low Byte)/ Load EEPROM Memory Page (page access) Byte 1 Byte 2 A Adr Bit 15 B 24.7 High-voltage Serial Programming This section describes how ...
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High-voltage Serial Programming Algorithm To program and verify the ATmega4HVD/8HVD in the High-voltage Serial Programming mode, the following sequence is recommended (See instruction formats in 24.8.1 Enter High-voltage Serial Programming Mode The following algorithm puts the device in (High-voltage) ...
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Chip Erase The Chip Erase will erase the Flash and EEPROM are not reset until the Program memory has been completely erased. The Fuse bits are not changed. A Chip Erase must be performed before the Flash and/or EEPROM ...
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Figure 24-4. High-voltage Serial Programming Waveforms SDI PB0 SII PB1 SDO PB2 SCI PB3 24.8.5 Programming the EEPROM The EEPROM is organized in pages, see EEPROM, the data is latched into a page buffer. This allows one page of data ...
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Table 24-14. High-voltage Serial Programming Instruction Set for ATmega4HVD/8HVD Instruction Instr.1/5 SDI 0_1000_0000_00 Chip Erase SII 0_0100_1100_00 SDO x_xxxx_xxxx_xx SDI 0_0001_0000_00 Load “Write Flash” SII 0_0100_1100_00 Command SDO x_xxxx_xxxx_xx SDI 0_ bbbb_bbbb _00 SII 0_0000_1100_00 SDO x_xxxx_xxxx_xx Load Flash Page ...
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Table 24-14. High-voltage Serial Programming Instruction Set for ATmega4HVD/8HVD (Continued) Instruction Instr.1/5 SDI 0_bbbb_bbbb_00 Read SII 0_0000_1100_00 EEPROM Byte SDO x_xxxx_xxxx_xx SDI 0_0100_0100_00 Write Fuse SII 0_0100_1100_00 Low Bits SDO x_xxxx_xxxx_xx SDI 0_0010_0000_00 Write Lock Bits SII 0_0100_1100_00 SDO x_xxxx_xxxx_xx ...
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Operating Circuit Figure 25-1. Operating Circuit Diagram R P PV1 470 C P 0.1uF GND R SENSE 10m ATmega4HVD/8HVD NI Notes: 1. Optional. The chip can operate without Charge FET. 2. Optional. Only needed for External Protection Input. 3. ...
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Electrical Characteristics Absolute Maximum Ratings* Operating Temperature.................................... -20°C to +85°C Storage Temperature ..................................... -65°C to +150°C Voltage on PB0 - PB2, VCC, and NI with respect to Ground ............................. -0.5V to VCC +0.5V Voltage on PV1 and BATT with ...
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Table 26-1. Electrical Characteristics Parameter Regulated Output Voltage, VREG (Linear regulation mode) Regulator Output Voltage, VREG (Force mode) Operating Voltage, VFET Voltage Regulator Regulator Force mode level (V ) FORCE Regulator Force level hysteresis Regulator drop in Force mode (VFET ...
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System and Reset Characteristics Table 26-2. Power-on, Reset, BLOD, and Voltage Reference Characteristics (unless otherwise noted) Symbol Parameter V Power-on Threshold Voltage POT V RESET Pin Threshold Voltage RST t Minimum pulse width on RESET Pin RST V BLOD ...
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General I/O Lines Characteristics Table 26- -20°C to 85°C, VFET = 2.1V to 4.2V (unless otherwise noted) A Symbol Parameter Input Low Voltage, Except ( RESET pin Input Low Voltage RESET V IL1 pin Input ...
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Table 26-6. FET Driver Outputs specification Parameter Condition (2) VFET DC level 1 cell DUVR operation (2) VFET ripple 1 cell DUVR operation OC, OD clamping voltage (3) OC, OD Normal ON operation OC, OD Normal OFF operation (2) Risetime ...
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ADC Characteristics Table 26-7. ADC Characteristics Symbol Parameter Resolution Absolute Accuracy (Including INL, DNL, Quantization Error, Gain and Offset Error) Integral Non-Linearity (INL) Differential Non-Linearity (DNL) Gain Error ADC Offset error PrescaledClock Frequency Conversion Time (VCELL, ADC0) Conversion Time (VTEMP) ...
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Programming Characteristics 26.6.1 Serial Programming Figure 26-1. Serial Programming Waveforms SERIAL DATA INPUT SERIAL DATA OUTPUT SERIAL CLOCK INPUT Figure 26-2. Serial Programming Timing Table 26-8. Serial Programming Characteristics, T Symbol Parameter 1/t Oscillator Frequency (ATmega4HVD/8HVD, V CLCL t ...
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High-voltage Serial Programming Figure 26-3. High-voltage Serial Programming Timing Table 26-9. Symbol t SHSL t SLSH t IVSH t SHIX t SHOV t WLWH_PFB 8052B–AVR–09/08 SDI , SII t IVSH SCI t SHSL SDO High-voltage Serial Programming Characteristics T ...
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Typical Characteristics – TBD The following charts show typical behavior. These figures are not tested during manufacturing. All current consumption measurements are performed with all I/O pins configured as inputs and with internal pull-ups enabled. A sine wave generator ...
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Register Summary Address Name Bit 7 (0xFF) Reserved – (0xFE) BPPLR – (0xFD) BPCR – (0xFC) Reserved – (0xFB) BPOCTR – (0xFA) BPSCTR – (0xF9) Reserved – (0xF8) Reserved – (0xF7) BPCOCD (0xF6) BPDOCD (0xF5) BPSCD (0xF4) Reserved – ...
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Address Name Bit 7 (0xBF) Reserved – (0xBE) Reserved – (0xBD) Reserved – (0xBC) Reserved – (0xBB) Reserved – (0xBA) Reserved – (0xB9) Reserved – (0xB8) Reserved – (0xB7) Reserved – (0xB6) Reserved – (0xB5) Reserved – (0xB4) Reserved – ...
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Address Name Bit 7 (0x7D) Reserved – (0x7C) Reserved – (0x7B) Reserved – (0x7A) ADCSRA ADEN (0x79) ADCH – (0x78) ADCL (0x77) Reserved – (0x76) Reserved – (0x75) Reserved – (0x74) Reserved – (0x73) Reserved – (0x72) Reserved – (0x71) ...
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Address Name Bit 7 0x1B (0x3B) Reserved – 0x1A (0x3A) Reserved – 0x19 (0x39) Reserved – 0x18 (0x38) Reserved – 0x17 (0x37) OSICSR – 0x16 (0x36) TIFR1 – 0x15 (0x35) TIFR0 – 0x14 (0x34) Reserved – 0x13 (0x33) Reserved – ...
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Instruction Set Summary Mnemonics Operands ARITHMETIC AND LOGIC INSTRUCTIONS ADD Rd, Rr Add two Registers ADC Rd, Rr Add with Carry two Registers ADIW Rdl,K Add Immediate to Word SUB Rd, Rr Subtract two Registers SUBI Rd, K Subtract ...
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Mnemonics Operands BRVC k Branch if Overflow Flag is Cleared BRIE k Branch if Interrupt Enabled BRID k Branch if Interrupt Disabled BIT AND BIT-TEST INSTRUCTIONS SBI P,b Set Bit in I/O Register CBI P,b Clear Bit in I/O Register ...
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Mnemonics Operands PUSH Rr Push Register on Stack POP Rd Pop Register from Stack MCU CONTROL INSTRUCTIONS NOP No Operation SLEEP Sleep WDR Watchdog Reset BREAK Break 8052B–AVR–09/08 Description STACK ← ← STACK (see specific descr. for Sleep ...
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... Power Supply MHz 2.0 - 2.4V Note: This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 18M1 18-pad (Staggered Dual-row) 6.5 x 3.5 x 0.80 mm Body. 3.20 x 2.00 mm Exposed Pad, (MLF) ATmega4HVD/8HVD ...
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... This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 18M1 18-pad (Staggered Dual-row) 6.5 x 3.5 x 0.80 mm Body. 3.20 x 2.00 mm Exposed Pad, (MLF) 8052B–AVR–09/08 Ordering Code Package ATmega8HVD-4MX 18M1 Package Type ATmega4HVD/8HVD Operation Range -20 - 85°C 159 ...
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Packaging Information 31.1 18M1 Pin TOP VIEW B10 BOTTOM VIEW 1. The terminal # Laser-marked Feature. Note: 2325 Orchard Parkway San Jose, CA 95131 ...
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... Errata 32.1 ATmega4HVD 32.1.1 All revisions No known errata. 32.2 ATmega8HVD 32.2.1 All revisions No known errata. 8052B–AVR–09/08 ATmega4HVD/8HVD 161 ...
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Datasheet Revision History 33.1 Rev 09/08 1. 33.2 Rev 09/08 1. ATmega4HVD/8HVD 162 Updated Table 20-2 on page 110 and mary of section of ”Battery Protection” on page Initial revision. Table 20-3 on page 111 ...
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Table of Contents Features ..................................................................................................... 1 1 Pin Configurations ................................................................................... 2 1.1Pin Descriptions .........................................................................................................3 2 Overview ................................................................................................... 4 3 Resources ................................................................................................. 5 4 Data Retention .......................................................................................... 5 5 About Code Examples ............................................................................. 5 6 AVR CPU Core .......................................................................................... 6 6.1Overview ...
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Clock Prescaler ........................................................................................25 8.11ADC Clock Prescaler .............................................................................................26 8.12OSI – Oscillator Sampling Interface ......................................................................27 8.13Register Description ..............................................................................................29 9 Power Management and Sleep Modes ................................................. 32 9.1Sleep Modes ............................................................................................................32 9.2Idle Mode .................................................................................................................34 9.3ADC Noise Reduction ..............................................................................................34 9.4Power-save Mode ....................................................................................................34 9.5Power-off Mode ...
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Description ..............................................................................................70 15 Timer/Counter0 and Timer/Counter1 Prescalers ................................ 71 15.1Overview ................................................................................................................71 15.2Internal Clock Source ............................................................................................71 15.3Prescaler Reset .....................................................................................................71 15.4External Clock Source ...........................................................................................72 15.5Register Description ..............................................................................................72 16 Timer/Counter(T/C0,T/C1) ...................................................................... 74 16.1Features ................................................................................................................74 16.2Overview ................................................................................................................74 16.3Timer/Counter Clock Sources ...............................................................................75 16.4Counter Unit ...
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Battery Protection ................................................................................ 104 20.1Features ..............................................................................................................104 20.2Overview ..............................................................................................................104 20.3Short-circuit Protection ........................................................................................105 20.4Discharge Over-current Protection ......................................................................105 20.5Charge Over-current Protection ..........................................................................105 20.6External Protection Input .....................................................................................106 20.7Battery Protection CPU Interface ........................................................................108 20.8Register Description ............................................................................................108 21 FET Control ........................................................................................... 114 21.1Overview ..............................................................................................................114 21.2FET ...
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... Register Summary ............................................................................... 151 29 Instruction Set Summary ..................................................................... 155 30 Ordering Information ........................................................................... 158 30.1ATmega4HVD .....................................................................................................158 30.2ATmega8HVD .....................................................................................................159 31 Packaging Information ........................................................................ 160 31.118M1 ....................................................................................................................160 32 Errata ..................................................................................................... 161 32.1ATmega4HVD .....................................................................................................161 32.2ATmega8HVD .....................................................................................................161 33 Datasheet Revision History ................................................................. 162 33.1Rev 09/08 ......................................................................................................162 33.2Rev 09/08 ......................................................................................................162 Table of Contents....................................................................................... i 8052B–AVR–09/08 ATmega4HVD/8HVD v ...
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... Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI- TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT ...