ATMEGA8HVD-4MX Atmel, ATMEGA8HVD-4MX Datasheet - Page 49

• Manufacturer Part Number: ATMEGA8HVD-4MX
• Description: MCU AVR 8K FLASH 2.1-8V 4MHZ QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA8HVD-4MX

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 4MHz
• Peripherals: POR, WDT
• Number Of I /o: 5
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 2.4 V
• Data Converters: A/D 1x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 18-MLF® Exposed Pad (Staggered Leads), DFN
• For Use With: ATSTK600 - DEV KIT FOR AVR/AVR32ATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Connectivity: -

8052B–AVR–09/08
If WDE is set, the Watchdog Timer is in Interrupt and System Reset Mode. The first timeout in
the Watchdog Timer will set WDIF. Executing the corresponding interrupt vector will clear
WDIE and WDIF automatically by hardware (the Watchdog goes to System Reset Mode). This
is useful for keeping the Watchdog Timer security while using the interrupt. To stay in Interrupt
and System Reset Mode, WDIE must be set after each interrupt. This should however not be
done within the interrupt service routine itself, as this might compromise the safety-function of
the Watchdog System Reset mode. If the interrupt is not executed before the next timeout, a
System Reset will be applied.
Table 10-1.
Note:
• Bit 5, 2..0 - WDP3..0 : Watchdog Timer Prescaler 3, 2, 1 and 0
The WDP3..0 bits determine the Watchdog Timer prescaling when the Watchdog Timer is
enabled. The different prescaling values and their corresponding Timeout Periods are shown
in
• Bit 4 - WDCE: Watchdog Change Enable
This bit is used in timed sequences for changing WDE and prescaler bits. To clear the WDE
bit, and/or change the prescaler bits, WDCE and WDE must be written to one. Within the next
four clock cycles, write the WDE and WDP bits as desired, and the WDCE bit cleared.
Once written to one, hardware will clear WDCE after four clock cycles.
• Bit 3 - WDE: Watchdog System Reset Enable
When the WDE bit is written to logic one, the Watchdog Timer is enabled, and if the WDE bit is
written to logic zero, the Watchdog Timer function is disabled. WDE can only be cleared if the
WDCE bit has logic level one, refer to the WDCE bit description.
If the WDTON fuse is programmed, it is not possible to disable the Watchdog Timer. Further-
more, WDE is overridden by WDRF in MCUSR. This means that WDE is always set when
WDRF is set. To clear WDE, WDRF must be cleared first. This feature ensures multiple resets
during conditions causing failure, and a safe start-up after the failure.
• Bits 5, 2..0 – WDP3..0: Watchdog Timer Prescaler 3, 2, 1, and 0
The WDP3..0 bits determine the Watchdog Timer prescaling when the Watchdog Timer is
enabled. The different prescaling values and their corresponding Timeout Periods are shown
in
WDTON
Table
Table
1
1
1
1
0
1. WDTON Fuse set to “0” means programmed, “1” means unprogrammed.
10-2.
10-2.
(1)
Watchdog Timer Configuration
WDE
0
0
1
1
x
WDIE
0
1
0
1
x
Mode
Stopped
Interrupt Mode
System Reset Mode
Interrupt and System Reset
Mode
System Reset Mode
ATmega4HVD/8HVD
Action on Timeout
None
Interrupt
Reset
Interrupt, then go to System
Reset Mode
Reset
49