ATMEGA8HVD-4MX Atmel, ATMEGA8HVD-4MX Datasheet - Page 10

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ATMEGA8HVD-4MX

Manufacturer Part Number
ATMEGA8HVD-4MX
Description
MCU AVR 8K FLASH 2.1-8V 4MHZ QFN
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheet

Specifications of ATMEGA8HVD-4MX

Core Processor
AVR
Core Size
8-Bit
Speed
4MHz
Peripherals
POR, WDT
Number Of I /o
5
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 2.4 V
Data Converters
A/D 1x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
18-MLF® Exposed Pad (Staggered Leads), DFN
For Use With
ATSTK600 - DEV KIT FOR AVR/AVR32ATSTK500 - PROGRAMMER AVR STARTER KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Connectivity
-
6.5
6.5.1
10
Stack Pointer
ATmega4HVD/8HVD
SPH and SPL – Stack pointer High and Low Register
Figure 6-3.
In the different addressing modes these address registers have functions as fixed displace-
ment, automatic increment, and automatic decrement (see the instruction set reference for
details).
The Stack is mainly used for storing temporary data, for storing local variables and for storing
return addresses after interrupts and subroutine calls. The Stack Pointer Register always
points to the top of the Stack. Note that the Stack is implemented as growing from higher
memory locations to lower memory locations. This implies that a Stack PUSH command
decreases the Stack Pointer.
The Stack Pointer points to the data SRAM Stack area where the Subroutine and Interrupt
Stacks are located. This Stack space in the data SRAM must be defined by the program
before any subroutine calls are executed or interrupts are enabled. The Stack Pointer must be
set to point above 0x100. The Stack Pointer is decremented by one when data is pushed onto
the Stack with the PUSH instruction, and it is decremented by two when the return address is
pushed onto the Stack with subroutine call or interrupt. The Stack Pointer is incremented by
one when data is popped from the Stack with the POP instruction, and it is incremented by two
when data is popped from the Stack with return from subroutine RET or return from interrupt
RETI.
The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The number of
bits actually used is implementation dependent. Note that the data space in some implementa-
tions of the AVR architecture is so small that only SPL is needed. In this case, the SPH
Register will not be present.
X-register
Y-register
Z-register
Bit
Read/Write
Initial Value
The X-, Y-, and Z-registers
SP15
R/W
R/W
SP7
15
7
0
1
15
7
R27 (0x1B)
15
7
R29 (0x1D)
15
7
R31 (0x1F)
SP14
R/W
SP6
R/W
14
6
0
1
SP13
SP5
R/W
R/W
XH
YH
ZH
0
13
5
0
1
SP12
R/W
R/W
SP4
12
4
0
1
0
0
SP11
R/W
R/W
SP3
11
3
0
1
7
R26 (0x1A)
7
R28 (0x1C)
7
R30 (0x1E)
SP10
SP2
R/W
R/W
10
2
0
1
XL
YL
ZL
SP1
R/W
R/W
SP9
9
1
1
1
0
R/W
R/W
SP8
SP0
8052B–AVR–09/08
8
0
0
1
0
0
0
0
0
SPH
SPL

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