ATMEGA8HVD-4MX Atmel, ATMEGA8HVD-4MX Datasheet - Page 48

• Manufacturer Part Number: ATMEGA8HVD-4MX
• Description: MCU AVR 8K FLASH 2.1-8V 4MHZ QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA8HVD-4MX

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 4MHz
• Peripherals: POR, WDT
• Number Of I /o: 5
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 2.4 V
• Data Converters: A/D 1x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 18-MLF® Exposed Pad (Staggered Leads), DFN
• For Use With: ATSTK600 - DEV KIT FOR AVR/AVR32ATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Connectivity: -

10.8
10.8.1
10.8.2
48
Register Description
ATmega4HVD/8HVD
MCUSR – MCU Status Register
WDTCSR – Watchdog Timer Control Register
The MCU Status Register provides information on which reset source caused an MCU reset.
• Bits 7:4, 2 – Res: Reserved Bits
These bits are reserved, and will always read as zero.
• Bit 4 – OCDRF: OCD Reset Flag
This bit is set if a debugWIRE Reset occurs. This bit is reset by a Power-on Reset, or by writ-
ing a logic zero to the flag.
• Bit 3 – WDRF: Watchdog Reset Flag
This bit is set if a Watchdog Reset occurs. The bit is reset by a Power-on Reset, or by writing
a logic zero to the flag.
• Bit 1 – EXTRF: External Reset Flag
This bit is set if an External Reset occurs. The bit is reset by a Power-on Reset, or by writing a
logic zero to the flag.
• Bit 0 – PORF: Power-on Reset Flag
This bit is set if a Power-on Reset occurs. The bit is reset only by writing a logic zero to the
flag.
To make use of the Reset flags to identify a reset condition, the user should read and then
reset the MCUSR as early as possible in the program. If the register is cleared before another
reset occurs, the source of the reset can be found by examining the reset flags.
• Bit 7 - WDIF: Watchdog Interrupt Flag
This bit is set when a timeout occurs in the Watchdog Timer and the Watchdog Timer is con-
figured for interrupt. WDIF is cleared by hardware when executing the corresponding interrupt
handling vector. Alternatively, WDIF is cleared by writing a logic one to the flag. When the I-bit
in SREG and WDIE are set, the Watchdog Timeout Interrupt is executed.
• Bit 6 - WDIE: Watchdog Interrupt Enable
When this bit is written to one and the I-bit in the Status Register is set, the Watchdog Interrupt
is enabled. If WDE is cleared in combination with this setting, the Watchdog Timer is in Inter-
rupt Mode, and the corresponding interrupt is executed if timeout in the Watchdog Timer
occurs.
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
R
7
–
0
WDIF
R/W
7
0
R
6
–
0
WDIE
R/W
6
0
5
–
R
0
WDP3
R/W
5
0
OCDRF
R/W
4
0
WDCE
R/W
4
0
WDRF
R/W
(1)
3
WDE
R/W
3
X
2
–
R
0
WDP2
R/W
2
0
EXTRF
R/W
(1)
1
WDP1
R/W
1
0
WDP0
PORF
R/W
R/W
(1)
0
0
0
8052B–AVR–09/08
WDTCSR
MCUSR