P89CV51RC2FBC,557 NXP Semiconductors, P89CV51RC2FBC,557 Datasheet - Page 17

• Manufacturer Part Number: P89CV51RC2FBC,557
• Description: IC 80C51 MCU FLASH 64K 44-TQFP
• Manufacturer: NXP Semiconductors
• Series: 89Cr

Specifications of P89CV51RC2FBC,557

• Program Memory Type: FLASH
• Program Memory Size: 32KB (32K x 8)
• Package / Case: 44-TQFP, 44-VQFP
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: EBI/EMI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 32
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: P89CV5x
• Core: 80C51
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: SPI/UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Operating Supply Voltage: 4.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4255; 935284104557; P89CV51RC2FBC

NXP Semiconductors
P89CV51RB2_RC2_RD2_3
Product data sheet
6.3.1 Flash organization
6.3.2 Features
6.3 Flash memory
Following a reset condition, under normal conditions, the MCU will start executing code
from address 0000H in the user’s code memory. However if either the PSEN pin was LOW
when reset was exited, or the status bit = 1, the MCU will start executing code from the
boot address. The boot address is formed using the value of the boot vector as the high
byte of the address and 00H as the low byte.
The P89CV51RB2/RC2/RD2 program memory consists of a 16/32/64 kB block for user
code. The flash can be read or written in bytes and can be erased in 128-B pages. A chip
erase function will erase the entire user code memory and its associated security bits.
There are three methods for erasing or programming the flash memory that may be used.
First, the flash may be programmed or erased in the end-user application by calling
LOW-state routines through a common IAP entry point. Second, the on-chip ISP
bootloader may be invoked. This ISP bootloader will, in turn, call LOW-state routines
through the same common entry point that can be used by the end-user application.
Third, the flash may be programmed or erased using the parallel method by using a
commercially available EPROM programmer which supports this device.
Fig 6.
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Flash internal program memory with 128-B page erase.
Internal boot block, containing LOW-state IAP routines available to user code.
Boot vector allows user-provided flash loader code to reside anywhere in the flash
memory space, providing flexibility to the user.
Default loader providing ISP via the serial port, located in upper-end of program
memory.
Programming and erase over the full operating voltage range.
Read/Programming/Erase using ISP/IAP.
Power-on reset circuit
V
Rev. 03 — 25 August 2009
DD
10 F
8.2 k
C 2
C 1
P89CV51RB2/RC2/RD2
RST
XTAL2
XTAL1
V
002aaa543
DD
80C51 with 1 kB RAM, SPI
© NXP B.V. 2009. All rights reserved.
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