Z8F6422AR020SC2104 Zilog, Z8F6422AR020SC2104 Datasheet - Page 144

• Manufacturer Part Number: Z8F6422AR020SC2104
• Description: IC ENCORE MCU FLASH 64K 64LQFP
• Manufacturer: Zilog
• Series: Encore!® XP®r

Specifications of Z8F6422AR020SC2104

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 46
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 64-LQFP
• For Use With: 269-4678 - KIT DEV FOR Z8F642 MCU 44 PIN269-4677 - KIT DEV FOR Z8F642 MCU 28PIN269-4540 - KIT DEV FOR Z8 ENCORE 16K TO 64K
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: 269-3641

PS019921-0308
Input Sample Time
Multi-Master Operation
Slave Operation
(CLKPOL = 0)
(CLKPOL = 1)
In a multi-master SPI system, all SCK pins are tied together, all MOSI pins are tied
together and all MISO pins are tied together. All SPI pins must then be configured in
OPEN-DRAIN mode to prevent bus contention. At any one time, only one SPI device is
configured as the Master and all other SPI devices on the bus are configured as Slaves.
The Master enables a single Slave by asserting the SS pin on that Slave only. Then, the
single Master drives data out its SCK and MOSI pins to the SCK and MOSI pins on the
Slaves (including those which are not enabled). The enabled Slave drives data out its
MISO pin to the MISO Master pin.
For a Master device operating in a multi-master system, if the SS pin is configured as an
input and is driven Low by another Master, the COL bit is set to 1 in the SPI Status Regis-
ter. The COL bit indicates the occurrence of a multi-master collision (mode fault error con-
dition).
The SPI block is configured for SLAVE mode operation by setting the SPIEN bit to 1 and
the MMEN bit to 0 in the SPICTL register and setting the SSIO bit to 0 in the SPIMODE
MOSI
MISO
SCK
SCK
SS
Figure 25. SPI Timing When PHASE is 1
Bit7
Bit7
Bit6
Bit6
Bit5
Bit5
Bit4
Bit4
Bit3
Bit3
Z8 Encore! XP
Bit2
Bit2
Product Specification
Serial Peripheral Interface
Bit1
Bit1
®
F64XX Series
Bit0
Bit0
130