Z8F6422AR020SC2104 Zilog, Z8F6422AR020SC2104 Datasheet - Page 159

• Manufacturer Part Number: Z8F6422AR020SC2104
• Description: IC ENCORE MCU FLASH 64K 64LQFP
• Manufacturer: Zilog
• Series: Encore!® XP®r

Specifications of Z8F6422AR020SC2104

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 46
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 64-LQFP
• For Use With: 269-4678 - KIT DEV FOR Z8F642 MCU 44 PIN269-4677 - KIT DEV FOR Z8F642 MCU 28PIN269-4540 - KIT DEV FOR Z8 ENCORE 16K TO 64K
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: 269-3641

PS019921-0308
Write Transaction with a 7-Bit Address
Figure 28
indicate data transferred from the I
data transferred from the slaves to the I
Follow the steps below for a transmit operation to a 7-bit addressed slave:
1. Software asserts the IEN bit in the I
2. Software asserts the TXI bit of the I
3. The I
4. Software responds to the TDRE bit by writing a 7-bit slave address plus write bit (=0)
5. Software asserts the START bit of the I
6. The I
7. The I
8. After one bit of address has been shifted out by the SDA signal, the Transmit interrupt
9. Software responds by writing the transmit data into the I
10. The I
11. If the I
12. The I
S
to the I
register.
is asserted (TDRE = 1).
high period of SCL the I
Continue with
If the slave does not acknowledge, the Not Acknowledge interrupt occurs (NCKI bit is
set in the Status register, ACK bit is cleared). Software responds to the Not
Acknowledge interrupt by setting the STOP and FLUSH bits and clearing the TXI bit.
The I
NCKI bits. The transaction is complete (ignore the following steps).
I
Figure 28. 7-Bit Addressed Slave Data Transfer Format
2
C Data register.
Slave Address
2
2
2
2
2
2
displays the data transfer format for a 7-bit addressed slave. Shaded regions
C interrupt asserts, because the I
C Controller sends the START condition to the I
C Controller loads the I
C Controller shifts the rest of the address and write bit out by the SDA signal.
C Controller sends the STOP condition on the bus and clears the STOP and
C Controller loads the contents of the I
2
2
C slave sends an acknowledge (by pulling the SDA signal low) during the next
C Data register.
step
12.
W = 0
2
C Controller sets the ACK bit in the I
A
2
2
C Shift register with the contents of the I
C Controller to slaves and unshaded regions indicate
2
C Controller.
Data
2
2
C Control register.
C Control register to enable Transmit interrupts.
2
2
C Data register is empty
C Control register.
2
A
C Shift register with the contents of the
Z8 Encore! XP
Data
2
C slave.
2
C Data register.
Product Specification
A
2
C Status register.
Data
®
F64XX Series
2
C Data
I2C Controller
A/A P/S
145