MC68HC705C8ACFN Freescale Semiconductor, MC68HC705C8ACFN Datasheet - Page 126

• Manufacturer Part Number: MC68HC705C8ACFN
• Description: IC MCU 4MHZ 8K OTP 44-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC05r

Specifications of MC68HC705C8ACFN

• Core Processor: HC05
• Core Size: 8-Bit
• Speed: 2.1MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 24
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: OTP
• Ram Size: 304 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -

Serial Communications Interface (SCI)
Technical Data
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Freescale Semiconductor, Inc.
For More Information On This Product,
Break Characters — Writing a logic 1 to the SBK bit in SCCR2
loads the shift register with a break character. A break character
contains all logic 0s and has no start and stop bits. Break
character length depends on the M bit in SCCR1. As long as SBK
is at logic 1, transmitter logic continuously loads break characters
into the shift register. After software clears the SBK bit, the shift
register finishes transmitting the last break character and then
transmits at least one logic 1. The automatic logic 1 at the end of
a break character is to guarantee the recognition of the start bit of
the next character.
Idle Characters — An idle character contains all logic 1s and has
no start or stop bits. Idle character length depends on the M bit in
SCCR1. The preamble is a synchronizing idle character that
begins every transmission.
Clearing the TE bit during a transmission relinquishes the
PD1/TDO pin after the last character to be transmitted is shifted
out. The last character may already be in the shift register, or
waiting in the SCDR, or it may be a break character generated by
writing to the SBK bit. Toggling TE from logic 0 to logic 1 while the
last character is in transmission generates an idle character (a
preamble) that allows the receiver to maintain control of the
PD1/TDO pin.
Transmitter Interrupts — These sources can generate SCI
transmitter interrupt requests:
– Transmit Data Register Empty (TDRE) — The TDRE bit in the
– Transmission Complete (TC) — The TC bit in the SCSR
Serial Communications Interface (SCI)
SCSR indicates that the SCDR has transferred a character to
the transmit shift register. TDRE is a source of SCI interrupt
requests. The transmission complete interrupt enable bit
(TCIE) in SCCR2 is the local mask for TDRE interrupts.
indicates that both the transmit shift register and the SCDR are
empty and that no break or idle character has been generated.
TC is a source of SCI interrupt requests. The transmission
complete interrupt enable bit (TCIE) in SCCR2 is the local
mask for TC interrupts.
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MC68HC705C8A — Rev. 3
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