MC68HC705C8ACFN Freescale Semiconductor, MC68HC705C8ACFN Datasheet - Page 73

• Manufacturer Part Number: MC68HC705C8ACFN
• Description: IC MCU 4MHZ 8K OTP 44-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC05r

Specifications of MC68HC705C8ACFN

• Core Processor: HC05
• Core Size: 8-Bit
• Speed: 2.1MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 24
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: OTP
• Ram Size: 304 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -

6.3.4 Non-Programmable COP Watchdog in Stop Mode
6.4 Wait Mode
MC68HC705C8A — Rev. 3
MOTOROLA
NOTE:
The STOP instruction has these effects on the non-programmable COP
watchdog:
If the RESET pin brings the MCU out of stop mode, the COP watchdog
begins counting immediately. The reset function clears the COP counter
again after the 4064-t
If the IRQ pin brings the MCU out of stop mode, the COP watchdog
begins counting immediately. The IRQ function does not clear the
COP counter again after the 4064-t
Figure
If the clock monitor is enabled (CME = 1), the STOP instruction causes
it to time out and reset the MCU.
The WAIT instruction places the MCU in an intermediate power
consumption mode. All central processor unit (CPU) activity is
suspended, but the oscillator, capture/compare timer, SCI, and SPI
remain active. Any interrupt or reset brings the MCU out of wait mode.
See
The WAIT instruction has these effects on the CPU:
The WAIT instruction does not affect any other registers or I/O lines. The
capture/compare timer, SCI, and SPI can be enabled to allow a periodic
exit from wait mode.
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Freescale Semiconductor, Inc.
Figure
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Turns off the oscillator and the COP watchdog counter
Clears the COP watchdog counter
Clears the I bit in the condition code register, enabling interrupts
Stops the CPU clock, but allows the internal clock to drive the
capture/compare timer, SCI, and SPI
6-3.
6-1.
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Low-Power Modes
CYC
clock stabilization delay.
CYC
clock stabilization delay. See
Low-Power Modes
Technical Data
Wait Mode
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