C8051F321R Silicon Laboratories Inc, C8051F321R Datasheet - Page 168

• Manufacturer Part Number: C8051F321R
• Description: IC 8051 MCU 16K FLASH 28MLP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F32xr

Specifications of C8051F321R

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 21
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 13x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: 336-1067-2

C8051F320/1
168
Bit7:
Bit6:
Bit5:
Bit4:
Bit3:
Bit2:
Bit1:
Bit0:
Bit7
Figure 15.22. EINCSRL: USB0 IN Endpoint Control High Byte (USB Register)
R
-
Unused. Read = 0; Write = don’t care.
CLRDT: Clear Data Toggle.
Write: Software should write ‘1’ to this bit to reset the IN Endpoint data toggle to ‘0’.
Read: This bit always reads ‘0’.
STSTL: Sent Stall
Hardware sets this bit to ‘1’ when a STALL handshake signal is transmitted. The FIFO is flushed, and
the INPRDY bit cleared. This flag must be cleared by software.
SDSTL: Send Stall.
Software should write ‘1’ to this bit to generate a STALL handshake in response to an IN token. Soft-
ware should write ‘0’ to this bit to terminate the STALL signal. This bit has no effect in ISO mode.
FLUSH: FIFO Flush.
Writing a ‘1’ to this bit flushes the next packet to be transmitted from the IN Endpoint FIFO. The
FIFO pointer is reset and the INPRDY bit is cleared. If the FIFO contains multiple packets, software
must write ‘1’ to FLUSH for each packet. Hardware resets the FLUSH bit to ‘0’ when the FIFO flush
is complete.
UNDRUN: Data Underrun.
The function of this bit depends on the IN Endpoint mode:
ISO: Set when a zero-length packet is sent after an IN token is received while bit INPRDY = ‘0’.
Interrupt/Bulk: Set when a NAK is returned in response to an IN token.
This bit must be cleared by software.
FIFONE: FIFO Not Empty.
0: The IN Endpoint FIFO is empty.
1. The IN Endpoint FIFO contains one or more packets.
INPRDY: In Packet Ready.
Software should write ‘1’ to this bit after loading a data packet into the IN Endpoint FIFO. Hardware
clears INPRDY due to any of the following:
1. A data packet is transmitted.
2. Double buffering is enabled (DBIEN = ‘1’) and there is an open FIFO packet slot.
3. If the endpoint is in Isochronous Mode (ISO = ‘1’) and ISOUD = ‘1’, INPRDY will read ‘0’ until
the next SOF is received.
An interrupt (if enabled) will be generated when hardware clears INPRDY as a result of a
packet being transmitted.
CLRDT
Bit6
W
STSTL
R/W
Bit5
SDSTL
R/W
Bit4
Rev. 1.1
FLUSH
Bit3
W
UNDRUN
R/W
Bit2
FIFONE
R/W
Bit1
INPRDY
R/W
Bit0
USB Address:
00000000
Reset Value
0x11