C8051F321R Silicon Laboratories Inc, C8051F321R Datasheet - Page 181

• Manufacturer Part Number: C8051F321R
• Description: IC 8051 MCU 16K FLASH 28MLP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F32xr

Specifications of C8051F321R

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 21
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 13x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: 336-1067-2

Figure 16.4 shows the typical SCL generation described by Equation 16.2. Notice that T
large as T
slave devices, or driven low by contending master devices). The bit rate when operating as a master will never exceed
the limits defined by equation Equation 16.1.
Setting the EXTHOLD bit extends the minimum setup and hold times for the SDA line. The minimum SDA setup
time defines the absolute minimum time that SDA is stable before SCL transitions from low-to-high. The minimum
SDA hold time defines the absolute minimum time that the current SDA value remains stable after SCL transitions
from high-to-low. EXTHOLD should be set so that the minimum setup and hold times meet the SMBus Specification
requirements of 250 ns and 300 ns, respectively. Table 16.2 shows the minimum setup and hold times for the two
EXTHOLD settings. Setup and hold time extensions are typically necessary when SYSCLK is above 10 MHz.
With the SMBTOE bit set, Timer 3 should be configured to overflow after 25 ms in order to detect SCL low timeouts
(see
SCL is high, and allow Timer 3 to count when SCL is low. The Timer 3 interrupt service routine should be used to
reset SMBus communication by disabling and re-enabling the SMBus.
SMBus Free Timeout detection can be enabled by setting the SMBFTE bit. When this bit is set, the bus will be con-
sidered free if SDA and SCL remain high for more than 10 SMBus clock source periods (see Figure 16.4). When a
Free Timeout is detected, the interface will respond as if a STOP was detected (an interrupt will be generated, and
STO will be set).
Timer Source
Section “16.3.3. SCL Low Timeout” on page
Overflows
LOW
SCL
EXTHOLD
†
occurs between the time SMB0DAT or ACK is written and when SI is cleared. Note that if
SI is cleared in the same write that defines the outgoing ACK value, s/w delay is zero.
. The actual SCL output may vary due to other devices on the bus (SCL may be extended low by slower
Setup Time for ACK bit transmissions and the MSB of all data transfers. The s/w delay
0
1
T
Low
Table 16.2. Minimum SDA Setup and Hold Times
Figure 16.4. Typical SMBus SCL Generation
Minimum SDA Setup Time
1 system clock + s/w delay
T
low
11 system clocks
- 4 system clocks
T
High
OR
178). The SMBus interface will force Timer 3 to reload while
Rev. 1.1
†
Minimum SDA Hold Time
SCL High Timeout
12 system clocks
3 system clocks
C8051F320/1
HIGH
is typically twice as
181