C8051F321R Silicon Laboratories Inc, C8051F321R Datasheet - Page 208

• Manufacturer Part Number: C8051F321R
• Description: IC 8051 MCU 16K FLASH 28MLP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F32xr

Specifications of C8051F321R

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 21
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 13x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: 336-1067-2

C8051F320/1
18.5. Serial Clock Timing
Four combinations of serial clock phase and polarity can be selected using the clock control bits in the SPI0 Configu-
ration Register (SPI0CFG). The CKPHA bit (SPI0CFG.5) selects one of two clock phases (edge used to latch the
data). The CKPOL bit (SPI0CFG.4) selects between an active-high or active-low clock. Both master and slave
devices must be configured to use the same clock phase and polarity. SPI0 should be disabled (by clearing the SPIEN
bit, SPI0CN.0) when changing the clock phase or polarity. The clock and data line relationships for master mode are
shown in Figure 18.5. For slave mode, the clock and data relationships are shown in Figure 18.6 and Figure 18.7.
Note that CKPHA must be set to ‘0’ on both the master and slave SPI when communicating between two of the fol-
lowing devices: C8051F04x, C8051F06x, C8051F12x, C8051F31x, C8051F32x, and C8051F33x
The SPI0 Clock Rate Register (SPI0CKR) as shown in Figure 18.10 controls the master mode serial clock frequency.
This register is ignored when operating in slave mode. When the SPI is configured as a master, the maximum data
transfer rate (bits/sec) is one-half the system clock frequency or 12.5 MHz, whichever is slower. When the SPI is con-
figured as a slave, the maximum data transfer rate (bits/sec) for full-duplex operation is 1/10 the system clock fre-
quency, provided that the master issues SCK, NSS (in 4-wire slave mode), and the serial input data synchronously
with the slave’s system clock. If the master issues SCK, NSS, and the serial input data asynchronously, the maximum
data transfer rate (bits/sec) must be less than 1/10 the system clock frequency. In the special case where the master
only wants to transmit data to the slave and does not need to receive data from the slave (i.e. half-duplex operation),
the SPI slave can receive data at a maximum data transfer rate (bits/sec) of 1/4 the system clock frequency. This is
provided that the master issues SCK, NSS, and the serial input data synchronously with the slave’s system clock.
208
NSS (Must Remain High
in Multi-Master Mode)
SCK
(CKPOL=0, CKPHA=0)
SCK
(CKPOL=0, CKPHA=1)
SCK
(CKPOL=1, CKPHA=0)
SCK
(CKPOL=1, CKPHA=1)
MISO/MOSI
Figure 18.5. Master Mode Data/Clock Timing
MSB
Bit 6
Bit 5
Rev. 1.1
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0