C8051F321R Silicon Laboratories Inc, C8051F321R Datasheet - Page 248

• Manufacturer Part Number: C8051F321R
• Description: IC 8051 MCU 16K FLASH 28MLP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F32xr

Specifications of C8051F321R

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 21
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 13x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: 336-1067-2

C8051F320/1
20.4. Register Descriptions for PCA
Following are detailed descriptions of the special function registers related to the operation of the PCA.
248
Bit7:
Bit6:
Bit5:
Bit4:
Bit3:
Bit2:
Bit1:
Bit0:
R/W
Bit7
CF
CF: PCA Counter/Timer Overflow Flag.
Set by hardware when the PCA Counter/Timer overflows from 0xFFFF to 0x0000. When the
Counter/Timer Overflow (CF) interrupt is enabled, setting this bit causes the CPU to vector to the
PCA interrupt service routine. This bit is not automatically cleared by hardware and must be cleared
by software.
CR: PCA Counter/Timer Run Control.
This bit enables/disables the PCA Counter/Timer.
0: PCA Counter/Timer disabled.
1: PCA Counter/Timer enabled.
UNUSED. Read = 0b, Write = don't care.
CCF4: PCA Module 4 Capture/Compare Flag.
This bit is set by hardware when a match or capture occurs. When the CCF4 interrupt is enabled, set-
ting this bit causes the CPU to vector to the PCA interrupt service routine. This bit is not automati-
cally cleared by hardware and must be cleared by software.
CCF3: PCA Module 3 Capture/Compare Flag.
This bit is set by hardware when a match or capture occurs. When the CCF3 interrupt is enabled, set-
ting this bit causes the CPU to vector to the PCA interrupt service routine. This bit is not automati-
cally cleared by hardware and must be cleared by software.
CCF2: PCA Module 2 Capture/Compare Flag.
This bit is set by hardware when a match or capture occurs. When the CCF2 interrupt is enabled, set-
ting this bit causes the CPU to vector to the PCA interrupt service routine. This bit is not automati-
cally cleared by hardware and must be cleared by software.
CCF1: PCA Module 1 Capture/Compare Flag.
This bit is set by hardware when a match or capture occurs. When the CCF1 interrupt is enabled, set-
ting this bit causes the CPU to vector to the PCA interrupt service routine. This bit is not automati-
cally cleared by hardware and must be cleared by software.
CCF0: PCA Module 0 Capture/Compare Flag.
This bit is set by hardware when a match or capture occurs. When the CCF0 interrupt is enabled, set-
ting this bit causes the CPU to vector to the PCA interrupt service routine. This bit is not automati-
cally cleared by hardware and must be cleared by software.
R/W
CR
Bit6
Figure 20.11. PCA0CN: PCA Control Register
R/W
Bit5
-
CCF4
R/W
Bit4
Rev. 1.1
CCF3
R/W
Bit3
CCF2
R/W
Bit2
CCF1
R/W
Bit1
(bit addressable)
CCF0
R/W
Bit0
SFR Address:
00000000
Reset Value
0xD8