C8051F321R Silicon Laboratories Inc, C8051F321R Datasheet - Page 25

• Manufacturer Part Number: C8051F321R
• Description: IC 8051 MCU 16K FLASH 28MLP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F32xr

Specifications of C8051F321R

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 21
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 13x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: 336-1067-2

1.6.
C8051F320 devices include 25 I/O pins (three byte-wide Ports and one 1-bit-wide Port); C8051F321 devices include
21 I/O pins (two byte-wide Ports, one 4-bit-wide Port, and one 1-bit-wide Port). The C8051F320/1 Ports behave like
typical 8051 Ports with a few enhancements. Each Port pin may be configured as an analog input or a digital I/O pin.
Pins selected as digital I/Os may additionally be configured for push-pull or open-drain output. The “weak pull-ups”
that are fixed on typical 8051 devices may be globally disabled, providing power savings capabilities.
The Digital Crossbar allows mapping of internal digital system resources to Port I/O pins (See Figure 1.8). On-chip
counter/timers, serial buses, HW interrupts, comparator outputs, and other digital signals in the controller can be con-
figured to appear on the Port I/O pins specified in the Crossbar Control registers. This allows the user to select the
exact mix of general purpose Port I/O and digital resources needed for the particular application.
1.7.
The C8051F320/1 Family includes an SMBus/I
tion, and an Enhanced SPI interface. Each of the serial buses is fully implemented in hardware and makes extensive
use of the CIP-51's interrupts, thus requiring very little CPU intervention.
Programmable Digital I/O and Crossbar
Serial Ports
Highest
Priority
Lowest
Priority
SYSCLK
Outputs
Outputs
SMBus
T0, T1
UART
P0
P1
P2
P3
CP0
CP1
PCA
SPI
(P0.0-P0.7)
(P1.0-P1.7)
(P2.0-P2.7)
(P3.0)
Figure 1.8. Digital Crossbar Diagram
2
4
2
2
2
6
2
8
8
8
8
2
C interface, a full-duplex UART with enhanced baud rate configura-
PnSKIP Registers
XBR0, XBR1,
Crossbar
Rev. 1.1
Decoder
Priority
Digital
8
8
8
1
PnMDIN Registers
PnMDOUT,
Cells
Cells
Cells
Cells
Note: P2.4-P2.7 only available
I/O
I/O
I/O
I/O
P0
P1
P2
P3
on the C8051F320
C8051F320/1
P0.0
P0.7
P1.0
P1.7
P2.0
P2.7
P3.0
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